Senior Timing Methodology Engineer, Custom Circuits

NVIDIA • Us, CA

11d

About The Position

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to resolve, that only we can seek, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and SoCs. This position is a broad opportunity to optimize performance, yield, and reliability through increasingly comprehensive modeling, informative analysis, and automation. This work will influence the entire next generation computing landscape through critical contributions across NVIDIA's many product lines ranging from consumer graphics to self-driving cars and the growing domain of artificial intelligence! We have crafted a team of highly motivated people whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. If you are fascinated by the immense scale of precision, craftsmanship, and artistry required to make billions of transistors function on every die at technology nodes as deep as 5 nm and beyond, this is an ideal role.

Requirements

• MS (or equivalent experience) in Electrical or Computer Engineering with 5+ years experience in ASIC Design and Timing.
• Proven understanding of circuit design and spice simulations.
• Hands-on experience in advanced CMOS technologies, design with FinFET technology 5nm/3nm/2nm and beyond.
• Good understanding of circuit design styles in CMOS: domino circuits, high speed clocking, clock muxing circuits etc and how to verify them at circuit level in both spice and transistor level sta.
• Understanding crosstalk, noise, OCV, timing margins.
• Familiarity with Clocking specs: jitter, IR drop, crosstalk, spice analysis.
• Should have a good understanding of .libs and usage of .libs in Nanotime as well as PT.
• Expertise in coding- TCL, Python.
• Must have hands-on experience with NanoTime static timing analysis, its algorithms and associated circuit constraint checks.
• Should be able navigate Cadence Virtuoso schematics.
• Familiarity with industry standard ASIC tools: PT, etc.
• Strong communications skill and good standout colleague

Responsibilities

• Develop Timing sign-off flows, constraints and QOR metrics for custom macro design at transistor level along with ones using standard cells and custom designs.
• Validating the timing of custom circuit design using NanoTime and various spice simulations.
• Validating ETM models
• The timing analysis will include the application of variation and statistical parameters in timing-analysis.
• The QOR data generation will include IR drop, PVT and impact of variation models POCV,AOCV, Moments, wire-variation etc.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Number of Employees: 5,001-10,000 employees