Senior ASIC Timing Engineer

NVIDIA•Austin, CA

About The Position

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of something great, join us today! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing! More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to tackle, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence. What you'll be doing: Drive timing analysis and closure of Nvidia’s GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level. Work with PD, DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints, driving timing and power convergence, as well as ECO implementation Apply knowledge and experience to improve timing convergence flows working with the methodology teams.

Requirements

BS (or equivalent experience) in Electrical or Computer Engineering with 5 years experience or MS (or equivalent experience) with 2 years experience in Timing and STA
Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation and management.
Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis.
Expertise and in-depth knowledge of industry standard STA and timing convergence tools.
Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes.

Nice To Haves

Background in domain specific STA and timing convergence, such as GPUs, CPUs, DPUs/Network processors, or SOCs
Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, BIST, etc.
Understanding and timing closure of digital logic/macros in AMS designs/IPs.
Experience in methodology and/or flow development as well as automation.

Responsibilities

Drive timing analysis and closure of Nvidia’s GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level.
Work with PD, DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints, driving timing and power convergence, as well as ECO implementation
Apply knowledge and experience to improve timing convergence flows working with the methodology teams.