Senior System-Manufacturing Co-Design Engineer

NVIDIA • Santa Clara, WA

1d • Hybrid

About The Position

Join NVIDIA, a trailblazer at the forefront of graphics and artificial intelligence performance, efficiency, and innovation. From our roots as a groundbreaking graphics company, we have evolved into a global leader in artificial intelligence, continuously pushing the boundaries to address sophisticated challenges across diverse industries. NVIDIA's Silicon Codesign Group (SCG) seeks a Senior System-Manufacturing Co-design Engineer to join our Arch team. We co-design system features and manufacturing flows to improve the voltage/frequency/power/thermal performance of our products. We find ways to ship a product with the highest TGP and Fmax, and the lowest Vmin possible, while minimizing overkill, miscorrelations, and test time. What you will be doing: Improving Voltage/Frequency/Power/Thermal Envelope of Nvidia Products Architect new Chip/System features to improve testable power, V/F, speed grades, temp, or test time Define the methodology for how manufacturing tests, SRAM, binning, or package technology constraints should be incorporated into product V/F curves, vmin, and TGP.

Requirements

• Master’s degree (MS) or equivalent experience in Electrical Engineering (EE), Computer Engineering (CE), Computer Science (CS), Systems Engineering, or a related field
• 8+ years of experience.
• Deep knowledge of System and chip circuits to improve DVFS, Binning, or Power/thermal management features for advanced SOCs/GPUs
• Comfortable in both the Pre-Silicon test strategy and hands-on lab prototyping of system features.
• Python/Perl Scripting

Nice To Haves

• Record of improving product performance through co-optimization with manufacturing

Responsibilities

• Improving Voltage/Frequency/Power/Thermal Envelope of Nvidia Products
• Architect new Chip/System features to improve testable power, V/F, speed grades, temp, or test time
• Define the methodology for how manufacturing tests, SRAM, binning, or package technology constraints should be incorporated into product V/F curves, vmin, and TGP.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level