Senior Staff Engineer, ASIC/VLSI Synthesis and Design

Marvell Technology•Irvine, CA

About The Position

We are seeking a highly skilled and experienced synthesis and ASIC front-end implementation Engineer to join our team. The ideal candidate will have a strong background in timing constraints development, synthesis and front-end implementation flows & methodologies for both SOC level and block level. They should have experience that includes logic synthesis (MMMC synthesis), logic equivalency checks, STA, timing constraints, functional ecos, hard IP integration, timing budgeting, optimization and timing closure of high-speed designs. Additionally, experience with deep technology nodes such as 5nm/4nm would be valued.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
Minimum of 5 years of industry experience in ASIC implementation and synthesis.
Strong understanding of ASIC design flows, from RTL to GDSII.
Knowledge and hands-on experience with synthesis and STA methodologies and implementation.
Proficiency in using synthesis tools, STA tools, and scripting languages (e.g., Tcl, Perl).
Strong understanding of timing constraint development for hierarchical designs.
Experience doing functional ECOs using industry standard tools and flows like Conformal ECO.
Experience with UPF development for blocks and SoCs.
Familiarity with physical design and timing optimization techniques and strategies to achieve timing closure.
Excellent problem-solving skills, attention to detail, and ability to analyze and debug complex issues.
Strong communication and collaboration skills to work effectively within cross-functional teams.

Nice To Haves

Experience with high-complexity silicon in advanced technology nodes, preferably TSMC N4/N5.
UPF validation using tools like Conformal Low Power (CLP)

Responsibilities

Develop and validate timing constraints for intricate SoC designs.
Collaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities, and develop consolidated timing modes and constraints for synthesis, PnR and chip timing sign-off flows.
Own and contribute to various Front-End Implementation tasks & flows like Synthesis, UPF development, Logical Equivalence Checks (LEC), Functional ECOs, etc.
Analyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows.
Perform Physical Aware Synthesis using industry-standard tools like Fusion Compiler.
Resolve or find workarounds for tool issues, independently or working with EDA tool vendors.
Automate Front End Flows and processes using scripting languages such as Tcl or Python.
Ensure compliance with Netlist Handoff checklists and criteria for delivery to PD.
Document best practices and lessons learned to drive continuous improvements in future projects.