Staff Engineer, IP Design (ASIC)

SK hynix memory solutions America Inc.•San Jose, CA

2d•$158,000 - $170,000

About The Position

At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape. We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing. You will join the System on Chip (SoC) Design Team at SK Hynix memory solutions America, a group dedicated to delivering best-in-class controllers for high-performance SSDs. This team spans the full design cycle—from micro-architecture and RTL design to timing closure and tapeout readiness—enabling next-generation enterprise and AI data center storage solutions. As a Staff Engineer, you will own critical High speed interface IP, drive methodology improvements (such as AI-assisted design flows), and mentor engineers to ensure first-pass silicon success.

Requirements

8 years of experience in ASIC design and deep knowledge in the design and integration of PCle logic.
Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl.
Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition.
Experience with Clock Domain Crossing (CDC), timing closure, or synthesis flows.

Nice To Haves

Experience in PCle(Gen4/5/6) architecture in TLP/FLIT pipelines, flow control, ordering rules, and performance tuning.
Proven experience with Link training, power state(L0/L0P/L1/L2), error handling (AER).
Experience with cross-functional leadership, driving efforts with software/system teams from RTL development through silicon bring-up.
Good plus to have experience in AI Assist design flow.

Responsibilities

Design and verification of the high speed interface for next generation storage subsystem for NVME or Chiplet.
Drive team efforts with multi-function teams from RTL development through silicon bring-up.