Senior SoC Design Verification Engineer

Intel Corp.•Hillsboro, OR

31d•Onsite

About The Position

Do Something Wonderful! Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and has a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Who We Are DDG designs next generation client microprocessors. Our team delivers emulation models to enable pre silicon verification. Who You Are Your responsibilities will include but not be limited to: Adding support for new features/IPs into existing emulation models Learning architecture and microarchitecture by debugging failures to the root cause Developing high level (for example, C++/Python) modeling for RTL components Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design Building multiple emulation targets for an SoC Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models System level validation tasks such as using evaluation boards and FPGAs SOC level feature enabling/debug The ideal candidate should exhibit the following behavioral traits: Problem-solving skills Ability to multitask Strong written and verbal communication skills Ability to work in a dynamic and team-oriented environment

Requirements

The candidate must have a Bachelor's Degree in Computer Science, Computer Engineering or Electrical Engineering with 4+ years of relevant experience -OR- Master's Degree in Computer Science, Computer Engineering or Electrical Engineering 3+ years of relevant experience -OR- PhD in Computer Science, Computer Engineering or Electrical Engineering
Problem-solving skills
Ability to multitask
Strong written and verbal communication skills
Ability to work in a dynamic and team-oriented environment

Nice To Haves

Experience with reading and interpreting technical specs and Register Transfer Level (RTL) code
Experience with validation or testing experience, especially in a silicon design team
Experience with UNIX or Linux
Experience with IA-32 assembly and/or Verilog programming experience
Experience writing BFMs

Responsibilities

Adding support for new features/IPs into existing emulation models
Learning architecture and microarchitecture by debugging failures to the root cause
Developing high level (for example, C++/Python) modeling for RTL components
Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design
Building multiple emulation targets for an SoC
Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models
System level validation tasks such as using evaluation boards and FPGAs
SOC level feature enabling/debug

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.

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