Senior Reliability Engineer - LPU Packaging

NVIDIA • Santa Clara, CA

1d

About The Position

NVIDIA is looking for a Senior Reliability Engineer to join our LPU packaging team. NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. We've built an incredible legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing, an era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand and engage with the world! Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their life's work. Come join the team and see how you can make a lasting impact on the world!

Requirements

• MS/PhD in Electrical Engineering, Materials Science, Mechanical Engineering, or related field, or equivalent experience.
• 8+ years of relevant expiernce
• Strong background in IC packaging and board level reliability, with hands on experience in:
• Experience with BGA/FCBGA, 2.5D/3D integration, HBM or similar high power, high pin count packages
• Background with JEDEC device/package reliability standards (e.g., HTSL, TCT, UHAST, pre con, board level solder reliability)
• Knowledge in system‑level stress or SLT and interpreting logs/telemetry for reliability analysis.
• Solid understanding of FIT, MTTF/MTBF, AFR, and RAS concepts

Nice To Haves

• Demonstrated ability to lead cross‑functional efforts across design, package R&D, SI/PI, validation, QA, and operations.
• Experience with data center or cloud hardware and understanding of:
• Rack and cluster‑level availability targets and constraints.
• Familiar with how component FIT drive sparing, repair rate, and availability planning
• Strong communication: Able to present trade‑offs and reliability risks clearly to both technical and program stakeholders.

Responsibilities

• Own the package‑level reliability spec for assigned products
• Define qualification requirements and pass/fail criteria for device/package‑level reliability (e.g., HTSL, TCT, UHAST, pre‑conditioning, JESD22 methods) and Package‑on‑board / board‑level reliability (thermal cycling, shock/vibration, connector/cage interactions)
• Leads materials and stackup selection (substrate, solder alloy, underfill, mold, lid, TIM, etc.) and DFR trade‑offs for new packages and 2nd sources
• Evaluates thermo‑mechanical and SI/PI impact of those choices
• Analyzes qual and stress data (including HTOL, package qual, SLT/system stress) and convert to design / process/ material changes for next revision.
• Understands how the component FIT rolls up from component level to system level and overall availability requirement

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level