Senior Principal Engineer, Verification

Marvell Technology•Santa Clara, CA

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Digital IC Design Senior Principal Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a digital team of about eight people making a big impact on this organization, working on ultra-dense and performance Static Random Access Memory (SRAM) memory compilers. This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates. What You Can Expect • Design, develop, implement, verify, and document micro-architecture and RTL for complex power management integrated circuits. • Work closely with system and chip architects to design industrial quality implementations. • Participate in the full design development cycle, end-to-end, from writing micro-architecture docs, RTL coding, specifications of timing, closely work with design verification teams to review test plans and execution of test, ability to bring up block tests on silicon during lab testing, and maintenance of designed blocks and reusable IPs. • Produce comprehensive block uArchitecture and register Specs. • Schedule detailed reviews with cross-functional teams Evaluate and participate in improving design and verification methodologies. • Supervise or mentor other digital design engineers.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience. Master’s degree in Computer Science, Electrical Engineering or related fields with 10-12 years of experience. PhD in Computer Science, Electrical Engineering or related fields with 8-10 years of experience.
Creating micro-architectural specs from standards, architectural specifications.
System Verilog RTL coding with System Verilog Assertions.
Universal Verification Methodology.
Creating modular/reusable design components.
Embedded micro-controller systems.
Ability to multi-task and must be flexible and adaptable to a rapidly changing and demanding environment.
Demonstrated success in project leadership.

Nice To Haves

Experience in the following areas is a plus: Design for Automotive Safety (ASIL) I2C, SPI, SMBUS.
Mixed-signal simulation (Cadence AMS).
Knowledge of power conversions systems.

Responsibilities

Design, develop, implement, verify, and document micro-architecture and RTL for complex power management integrated circuits.
Work closely with system and chip architects to design industrial quality implementations.
Participate in the full design development cycle, end-to-end, from writing micro-architecture docs, RTL coding, specifications of timing, closely work with design verification teams to review test plans and execution of test, ability to bring up block tests on silicon during lab testing, and maintenance of designed blocks and reusable IPs.
Produce comprehensive block uArchitecture and register Specs.
Schedule detailed reviews with cross-functional teams Evaluate and participate in improving design and verification methodologies.
Supervise or mentor other digital design engineers.