Senior Physical Design Methodology Engineer, Retime Flows

NVIDIA • Santa Clara, CA

8d

About The Position

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer to solve challenging problems for the next generation technology and next generation high speed AI chips. Ideal candidate has in-depth understanding of Device Physics, Interconnect physics, hierarchical floorplanning, Place and route concepts. Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a meaningful, growing and professional environment where you make a significant impact in a technology-focused company.

Requirements

• MS in Electrical or Computer Engineering (or equivalent experience)
• Minimum 5 years experience in Physical Design Engineering
• Familiar with aspects of chip design including Floor planning, Clock and Power distribution, Place and Route, Integration and Verification.
• Strong background with hierarchical design approach, top-down design, budgeting, timing and physical convergence.
• Familiar with various process related design issues including Design for Yield and Manufacturability, EM and IR closure and thermal management.
• You'll need to have expertise and in-depth knowledge of industry standard EDA tools.
• Proficiency in programming and scripting languages, such as, Perl, Python, and C++.

Responsibilities

• Developing physical design methodologies for implementation of graphics processors and SOCs.
• Key responsibility includes developing unique and creative solutions to the state of the art physical design problems that are needed for NVIDIA chips.
• Participate in developing flow and tool methodologies for chip floorplan, power and clock distribution, chip assembly and P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees