Senior Physical Design Methodology Engineer, Innovus Flows

NVIDIA • Santa Clara, CA

8d

About The Position

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are looking for a physical design engineer to be a part of NVIDIA’s physical design (PD) methodology team driving innovation in PD across all of NVIDIA's products – Datacenter AI, HPC, Networking, Robotics, Autonomous driving, gaming and more. As the cadence of NVIDIA’s chip cycle shortens, it poses new challenges for physical design teams to not only deliver the best PPA on the chips, but to also do it at scale, in the shortest possible time. Your work in physical design methodology directly enables our speed to market in delivering industry’s leading chip hardware. This role provides a unique opportunity to innovate at the cutting edge of process technology, EDA tools, and PD flows through collaboration with RTL, synthesis, DFT, foundry, timing other cross functional teams to push the limits of physical design at scale.

Requirements

• MS in Electrical or Computer Engineering (or equivalent experience)
• Minimum 7 years of experience in Physical Design; emphasis on methodology and flow development is highly preferred
• Proven track record of PPA improvement on high performance and low power designs in advanced technology nodes
• Strong understanding of physical design optimization and routing methodologies at place, cts, route and postroute, especially power and area efficient setup and hold optimization
• Strong background in STA, extraction, timing and RC correlation
• Experience in low power design with UPF, and use of FSDB/SAIFs for power optimization
• Solid understanding of EM and IR analysis and closure
• Understanding of synthesis, hierarchical design, pinning and budgeting flows
• Experience with power distribution networks, EM/IR analysis and closure, Design for Yield and Manufacturability and thermal management
• Expertise and in-depth knowledge of industry standard EDA tools and proficiency in programming and scripting languages, such as TCL, Perl, Python, and C++

Nice To Haves

• Experience applying ML models, LLMs, and agentic AI techniques to EDA/PD problems (analytics, prediction, optimization)
• Proficiency with data analysis/ML libraries (e.g., NumPy, SciPy, scikit-learn, PyTorch, etc.)
• Proficiency in Cadence EDA tool suite – Innovus/genus/tempus/quantus/joules etc.

Responsibilities

• Developing innovative physical design methodologies for implementation of GPU, CPU, Network processors and SOC, with emphasis on PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes
• Work with internal and external partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all our product lines
• Use AI/ML approaches to CAD to improve design performance and turnaround time, while improving efficiency and productivity of designers

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees