Senior Physical Design Engineer - Circuits

NVIDIA • Santa Clara, CA

7d • Hybrid

About The Position

We are now looking for a Senior Physical Design Engineer in our Circuits Solutions Group! NVIDIA has been redefining computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s motivated by great technology, outstanding people and a multifaceted workforce! Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you will be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! What you'll be doing: Work as part of a global circuits team alongside custom circuit designers and custom mask designers to deliver physical designs of innovative circuits for hardware security, adaptive clocking, and power management solutions. Responsible for all aspects of physical design and implementation of custom macros for GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets. In this position, you will be expected to lead all custom circuit IP level PD activities for the macros assigned to you. You will have the unique opportunity to drive the physical implementation of custom mixed signal IPs using industry standard tools and novel custom AI automated place and route tools. Participate in establishing physical design methodologies, flow automation, floorplan, power/clock distribution, custom IP P&R, and timing closure. PD activities include floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. Will be required to work in collaboration with design team to address design challenges.

Requirements

• BSEE (MSEE preferred) or equivalent experience.
• 6+ years of experience in large VLSI physical design implementation on 5nm, 4nm and/or 3nm technology.
• Successful track record of delivering designs to production is a requirement.
• Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
• Good knowledge and experience in Block-level Floor-planning and Physical verification.
• Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation.
• Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred.
• Well versed with timing constraints, STA, and timing closure.
• Good automation skills in Python, PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools.
• Proficiency using Perl, Tcl, Make scripting is preferred.

Nice To Haves

• Excellent communication skills and strong motivation to drive projects to completion
• To be successful you should possess strong analytical and problem solving skills.
• Ability to multi-task and flexibility to work in global environment.
• Good understanding of process issues and digital circuit design techniques is a plus.
• Good understanding of transistor level fundamentals is a plus.

Responsibilities

• Work as part of a global circuits team alongside custom circuit designers and custom mask designers to deliver physical designs of innovative circuits for hardware security, adaptive clocking, and power management solutions.
• Responsible for all aspects of physical design and implementation of custom macros for GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets.
• Lead all custom circuit IP level PD activities for the macros assigned to you.
• Drive the physical implementation of custom mixed signal IPs using industry standard tools and novel custom AI automated place and route tools.
• Participate in establishing physical design methodologies, flow automation, floorplan, power/clock distribution, custom IP P&R, and timing closure.
• PD activities include floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification.
• Work in collaboration with design team to address design challenges.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees