Senior Physical Design Application Engineer

Intel Corporation • Hillsboro, OR

1d • Hybrid

About The Position

About Intel Foundry Intel Foundry is a systems foundry transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. Intel Foundry will be differentiated from other foundries by our world class industry-leading IP portfolio that customers can choose from including, rich IP ecosystem including x86 cores, graphics, AI, and Arm/RISC-V IPs, world-class design services, and operationally resilient global manufacturing with committed capacity in the US and Europe. Position Overview We seek a Senior Applications and Solutions Engineer to provide technical support to Intel Foundry Services customers on PDKs, digital reference flows, and design signoff methodologies with specialized focus on Cadence tool suites. This role drives quality improvements in design kits through ASIC design reference flow validation and supports customers through successful tape-outs.

Requirements

• US Citizenship required
• Ability to obtain a US Government Security Clearance
• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or STEM-related field of study
• 4+ years of experience with advanced CMOS processes (22nm and below)
• 3+ years of experience in ASIC physical design implementation and/or ASIC design signoff (SoC/ASIC)
• 3+ years of experience in one of the following scripting languages (i.e. Python, Perl, Tcl, shell scripting)

Nice To Haves

• Active US Government Security Clearance with a minimum of Secret level
• Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study
• Customer-facing experience in technical support roles
• Experience with state-of-the-art process technology (7nm and below)
• Hands-on experience in Cadence EDA-based ASIC design implementation including full-chip integration, synthesis, APR, static timing analysis, layout verification, and reliability verification
• Proficiency with Cadence EDA tools and flows: Innovus, Tempus, TempusECO, Pegasus, Voltus
• Experience with Synopsys tools (Fusion Compiler, PrimeTime, Prime ECO, ICV) is a plus
• Experience with hierarchical and multi-voltage domain design, top-down design, budgeting, and correlation across implementation and verification tools

Responsibilities

• Customer Technical Support & Implementation Provide comprehensive technical support to Intel Foundry Services customers on PDKs, digital reference flows, and digital design signoff methodologies
• Support and deliver ASIC/Digital tool/flow/methodology solutions using Cadence tool suites to address customer issues and ensure successful tape-outs
• Drive customer success through expert guidance on advanced CMOS process implementation
• Quality Assurance & Documentation Drive quality improvements in design kits and documentation through ASIC design reference flow validation and comprehensive documentation review
• Create application notes, technical content, and deliver training presentations to customers and internal teams
• Establish and maintain quality assurance processes for design flow validation
• Design Flow Development & Optimization Develop and optimize digital design implementation flows for advanced CMOS processes
• Support hierarchical and multi-voltage domain design approaches, timing and physical convergence
• Build and maintain quality assurance (QA) regression frameworks for design validation

Benefits

• We offer a total compensation package that ranks among the best in the industry.
• It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
• Find out more about the benefits of working at Intel.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level