Senior IP Logic Design Engineer

Intel Corporation • Santa Clara, CA

1d • Hybrid

About The Position

Embark with us on a journey of growth and transformation as we create exceptionally engineered technology and bring AI everywhere. As a valued team member, your adaptability and attention to detail will contribute to our drive for results and relentless pursuit of quality, ensuring we meet our customers' needs with precision. Join us and build on our legacy of innovation and collaboration as we deliver world‑changing technology that improves the life of every person on the planet. The ideal candidate will develop the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high-quality integration and verification of the IP block. Drives quality assurance compliance for smooth IPSoC handoff.

Requirements

• MS/PhD in Electrical Engineering, Computer Engineering, or related field.
• 10+ years in SoC design, including significant experience in memory systems, coherency protocols, and RTL coding and at least one or more of the following:
• Expertise in memory coherency protocols (e.g., MESI, MOESI, CXL, CCIX, CHI).
• Strong knowledge of interconnect technologies (e.g., AMBA, PCIe, NoC architectures).
• Proven RTL coding experience in Verilog or SystemVerilog.
• Proficiency in simulation tools for performance modeling and analysis.
• Familiarity with physical design implications of memory fabric architectures (timing, power, area).
• Experience with EDA tools for synthesis, linting, and static timing analysis.

Nice To Haves

• Hands-on experience with high-bandwidth memory (HBM), DDR, or other advanced memory technologies.
• Background in AI/ML accelerator or data center SoC design.
• Knowledge of scripting languages like Python or TCL for workflow automation.
• Experience with software-hardware co-design for end-to-end system optimization.

Responsibilities

• Architect scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs.
• Design and implement critical components of the memory fabric microarchitecture, including coherency controllers and interconnect blocks.
• Develop RTL code for core components of the memory fabric, ensuring optimal performance, area, and power trade-offs.
• Work closely with verification teams to create test plans and debug issues arising during pre-silicon validation.
• Collaborate with cross-functional teams (physical design, software, and firmware) to ensure seamless integration of memory fabric systems.
• Analyze system performance, conduct workload modeling, and optimize the architecture for target use cases.
• Mentor junior engineers and contribute to technical reviews and design documentation.
• Stay updated with emerging technologies and trends in memory subsystems, coherency protocols, and AI/ML hardware.

Benefits

• We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Ph.D. or professional degree
• Number of Employees: 5,001-10,000 employees