Senior Hardware Engineer

Tower Research Capital • New York, NY

20h • Hybrid

About The Position

Tower Research Capital is a leading quantitative trading firm founded in 1998, known for its high-performance platform and independent trading teams. With over 25 years of innovation, Tower focuses on discovering unique market opportunities. The firm prides itself on housing top systematic trading and engineering talent, empowering portfolio managers with economies of scale from a large, global organization. Engineers at Tower develop world-class electronic trading infrastructure, tackling challenging problems in low-latency programming, FPGA technology, hardware acceleration, and machine learning. Continuous investment in talent and technology ensures the platform's unmatched functionality, scalability, and performance. Business Support teams are crucial for building and maintaining this platform, enabling trading and engineering teams to excel. Tower offers a stimulating, results-oriented environment where intelligent and motivated colleagues inspire each other to reach their full potential.

Requirements

• A bachelor’s degree in electrical engineering, or equivalent professional experience
• At least 5 to 10 years of experience with ASIC and/or FPGA development
• Verilog or System Verilog programming
• ASIC development via VHDL or Verilog experience will qualify for the position
• Expert-level knowledge of FPGA products (Xilinx preferred), development tools, and related simulators
• Experience with Ethernet protocols, PCIe, and/or switching and routing in network equipment, parsing and traffic shaping.
• A strong understanding of network PHY interfacing
• Integration experience with independent third-party cores
• Able to design and develop signal processing cores from system and architectural requirements
• Ability to document design and interface specifications
• Experience in Linux environment
• Comfortable with shell scripting and one or more common scripting languages (e.g. Python)

Nice To Haves

• A demonstrated background in 100Mbps, 1Gbps, 10Gbps and 40Gbps network interfaces (preferred)
• An understanding of various network hardware techniques, such as store and forward (preferred)
• Previous work experience at a high-frequency trading firm (preferred)
• Experience with collaborating in a global team environment across regions and time zones (plus)
• Writing kernel drivers for FPGA (plus)
• C or C++ programming experience (plus)
• A strong background in mathematics (plus)

Responsibilities

• Collaborating with software developers across divisions to architect low-latency connections to financial exchanges around the world
• Building advanced Ethernet-based communication stacks direct from chip to SFP
• Integrating network stacks to connect to various financial exchanges
• Creating custom logic to manage a constant inflow of data, which will need to be parsed, processed, and passed to the user space in the most efficient manner possible
• Working closely with software developers to develop an optimal interface between FPGA hardware and user space software

Benefits

• Generous paid time off policies
• Savings plans and other financial wellness tools available in each region
• Hybrid working opportunities
• Free breakfast, lunch, and snacks daily
• In-office wellness experiences and reimbursement for select wellness expenses (e.g., gym, personal training and more)
• Company-sponsored sports teams and fitness events (JPM Corporate Challenge, Cycle for Survival, Wall Street Rides FAR and more)
• Volunteer opportunities and charitable giving
• Social events, happy hours, treats, and celebrations throughout the year
• Workshops and continuous learning opportunities

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Number of Employees: 501-1,000 employees