Senior Hardware Emulation Engineer

Google•Sunnyvale, CA

15h

About The Position

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. You will design and build the hardware, software, and networking technologies that power all of Google's services. You will be responsible for delivering the platform used for pre-silicon validation and verification of custom ASICs and enable a "shift left" of Software (SW) development and complement DV in our efforts to validate the ASICs. You will create emulated hardware environments of our chip Register-Transfer Level (RTL) with custom features and models unique to emulation and enable speedup over simulation and an integrated environment before silicon availability. You will create methodology, flows, automation, and designs through tapeout and beyond, own the deployment and maintenance of emulation hardware and physical infrastructure. You can be a part of this team, delivering high-value ASIC solutions to Google's infrastructure. You will work with team members as well as designers, verification engineers, and software teams. You will interface with our external vendors, lab support teams, networking and security, and EDA tooling and methodology teams to deliver emulation based prototyping capabilities for our ASIC projects. You may also assist in compiling projects targeting our prototyping platforms, debugging issues in both infrastructure and design, and assisting in the hardware and lab bring up and verification of our ASIC systems.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're behind Google's groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Requirements

Bachelor's degree in Electrical Engineering or a related field.
6 years of industry experience with RTL design (e.g., Verilog or System Verilog) and simulation (e.g., VCS, Incisive or Questa).
Experience with coding or scripting in C, C++, Perl, TCL or Python.
Experience with emulation systems (e.g., ZeBu, Palladium, Veloce), compilation, debugging, performance and methodology enhancements.

Nice To Haves

Master's degree in Electrical Engineering or a related field.
10 years of industry experience with RTL design (e.g., Verilog or System Verilog) and simulation (e.g., VCS, Incisive or Questa).
Experience with performance analysis/debug techniques.
Experience with simulation acceleration using transactors (DPI-C) or vendors provided accelerated verification IP.
Knowledge of external I/O interfaces like PCIe, DDR5, HBM, SPI, or JTAG etc.
Understanding of computer architecture including industry standard interfaces and memory subsystems.

Responsibilities

Drive system bring up on emulation platforms, debug test failures and simulation/emulation mismatches.
Bring up external I/O interfaces (e.g., PCIe, Memories, SERDES, SPI, JTAG etc.) on the emulation platforms.
Develop and operate tests on the emulators and assist in bring-up processes from prototyping through post-silicon validation.
Contribute to ongoing methodology and automation improvements, constantly evolving and improving emulation efficiency and value.
Create and support emulation models from RTL and create standalone test cases for tool issues encountered in the emulation compile and runtime flows.