Senior Engineer (7309)

TSMC • San Jose, CA

37d • Onsite

About The Position

Responsible for the senior level physical design and implementation of large-scale, low power, and high-performance ASIC chips using TSMC’s advanced technologies. Specific job duties include the following: Applying the principles of SoC (System on Chip) and high-speed low-power VLSI (Very Large Scaled Integrated-circuits) design to perform advanced chip physical design and implementation for TSMC’s advanced processing technology. Executing block level floor plan, clock tree synthesis, place and route, RC extraction (parasitic extraction), static timing analysis (STA) and timing closure. Performing IR/EM (voltage drop analysis/electro-migration)/Noise analysis and fix. DRC/LVS/ERC (Design Rule Check/Layout Versus Schematic/Electrical Rule Check) clean up, and tape-out sign off using Perl/TCL language programming. Supporting customers in advanced chip implementation.

Requirements

• Master’s degree or foreign equivalent in Electrical and Computer Engineering, Electronic Engineering or a related field.
• Knowledge of VLSI, and ASIC design including logic design, RTL design, layout design, and PHYSICAL DESIGN
• knowledge of critical areas including timing, power, performance, and area, noise and crosstalk, process variation impact, planar and FINFET technologies
• Experience with physical design verification such as  LVS/DRC including CMOS design rules
• Experience with EDI tools including cadence Virtuoso, ICC2, and Tetramax
• experience with EDI tool flow development using python/TCL language programming

Responsibilities

• Applying the principles of SoC (System on Chip) and high-speed low-power VLSI (Very Large Scaled Integrated-circuits) design to perform advanced chip physical design and implementation for TSMC’s advanced processing technology.
• Executing block level floor plan, clock tree synthesis, place and route, RC extraction (parasitic extraction), static timing analysis (STA) and timing closure.
• Performing IR/EM (voltage drop analysis/electro-migration)/Noise analysis and fix.
• DRC/LVS/ERC (Design Rule Check/Layout Versus Schematic/Electrical Rule Check) clean up, and tape-out sign off using Perl/TCL language programming.
• Supporting customers in advanced chip implementation.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Number of Employees: 5,001-10,000 employees