Senior Engineer Package Designer

The PJF Group • San Jose Bay Area, CA

17h

About The Position

We are seeking a Senior Package Design Engineer to join our custom SOC/ASIC development client. You'll work closely with cross-functional teams in the U.S. and overseas on high-performance package substrate design with a focus on signal/power integrity and routing. Why is This a Great Opportunity This is an outstanding technology, great opportunity to learn. Growing company with a lot of IP. Everyone contributes.

Requirements

• BS in EE or related field; MS preferred
• 8–10 years of experience in semiconductor package design
• Strong SI/PI analysis, modeling, and simulation skills
• Excellent communication, teamwork, and presentation abilities

Nice To Haves

• Expertise in high-speed package/PCB design (SerDes, PCIe, LPDDR, Ethernet)
• Time/frequency domain analysis, impedance, jitter, eye-diagram, BER analysis
• Experience with Hspice, Redhawk, electro-thermal simulation, PDN modeling
• Familiarity with reliability analysis and packaging/assembly rules

Responsibilities

• Perform package substrate design and analysis (SI/PI/routing)
• Collaborate with layout engineers, marketing, and global design teams
• Use tools like HFSS, ADS for package modeling/simulation
• Contribute during pre/post-sales processes

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level