Senior Engineer, DFT

Celestial AI • Santa Clara, CA

18h • $200,000 - $220,000 • Onsite

About The Position

We are seeking a Senior DFT Engineer with 5+ years of hands-on implementation experience across MBIST, BISR, Boundary Scan, and IJTAG. This is a highly execution-driven role requiring end-to-end ownership of DFT insertion, verification, DRC closure, and test coverage closure from RTL/netlist through post-silicon debug.
In this role, you will partner closely with RTL, Physical Design, and ATE teams to deliver clean DFT signoff and robust test coverage for complex SoC designs

Requirements

• Bachelor’s degree with 6+ years of relevant experience, or Master’s degree with 5+ years of relevant experience
• 5+ years of hands-on DFT implementation experience
• Strong proficiency with Siemens Tessent, including:
• MBIST / BISR insertion and verification
• Boundary Scan (IEEE 1149.x)
• IJTAG (IEEE 1687)
• ATPG pattern generation and coverage analysis
• Proven ability to resolve DFT DRCs, connectivity issues, and testability problems
• Strong TCL scripting skills for DFT automation and flow execution
• Experience developing and validating scan and test-mode timing constraints
• End-to-end DFT lifecycle experience, from RTL/netlist through silicon debug
• Strong debugging skills, attention to detail, and sense of ownership
• Excellent verbal and written communication skills

Nice To Haves

• Experience driving MBIST coverage improvement and repair efficiency optimization
• Post-silicon experience, including:
• Pattern bring-up and debug
• Tester pattern conversion
• Silicon characterization
• Exposure to mixed-signal or SERDES DFT, such as IOBIST or loopback testing

Responsibilities

• Perform hands-on DFT implementation, including:
• MBIST and BISR insertion and integration
• Boundary Scan (IEEE 1149.x) insertion
• IJTAG (IEEE 1687) insertion and connectivity
• Execute DFT verification, debug, and DFT DRC closure using Siemens Tessent
• Identify, debug, and resolve DFT rule violations at both block and top levels
• Run, analyze, and debug SpyGlass DFT/RTL checks, working with design teams to close violations
• Generate, simulate, and debug MBIST and logic ATPG patterns
• Analyze test results and drive test coverage improvement and closure
• Develop and validate DFT timing constraints for scan, BIST, and test modes
• Create and maintain TCL scripts to automate DFT insertion, verification, and analysis flows
• Support hierarchical DFT implementation and resolve integration issues
• Collaborate with RTL and Physical Design teams to address DFT-related design issues
• Support pre-silicon DFT signoff and assist with post-silicon pattern bring-up and debug
• Assist with ATE pattern conversion and debug as needed

Benefits

• health, vision, dental and life insurance
• collaborative and continuous learning work environment
• chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 101-250 employees