Senior Director / Vice President of Software Engineering – Front-End Design Tools & AI Acceleration (EDA + Agentic AI)

Altera•San Jose, CA

67d

About The Position

We’re seeking a Senior Director or Vice President of Software Engineering (title commensurate with experience) to lead the development of Altera’s flagship FPGA design platform — Quartus! This is a high-impact leadership role with a dual mandate: Delivering world-class front-end EDA tools, and Reimagining the FPGA development experience in the AI era — including AI-accelerated workloads and agentic design experiences. You’ll lead a talented, mission-driven engineering team (~100+ engineers), manage a diverse suite of tools, and help drive a transformative AI-first strategy that positions FPGAs at the center of tomorrow’s compute stack. Your Mission -Drive the Future of Agentic, AI-Powered Design -Lead the transformation toward intelligent and contextual development environments, powered by the latest in AI/LLM technology. Define the vision for AI-assisted design using LLMs and agentic workflows Build IDE integrations and tooling copilots tailored for FPGA developers Partner closely with product, UX, and AI platform teams to deliver seamless, intelligent experiences -Lead and Scale a World-Class EDA Tooling Team -Oversee the full-stack development of Quartus front-end tools, including: Design entrance (schematic/coding interfaces) GUI frameworks IP integration and reuse Timing analysis and debug environments Core infrastructure and design databases -Foster technical excellence, reliable execution, and high product quality. Build a culture of innovation and ownership across the team. -Enable AI Acceleration Through Smarter FPGA Development -Accelerating AI workloads is a priority — and FPGA design must evolve to meet it. You will: Collaborate with architecture and hardware teams to ensure the front-end tooling supports AI acceleration use cases, including custom dataflow and ML model mapping Drive integration of AI-specific IPs, reference designs, and optimization flows Ensure the design environment is intuitive and scalable for engineers building AI/ML solutions on FPGAs

Requirements

Proven leadership of large-scale engineering teams (preferably 50+ engineers)
Deep understanding of EDA tools and FPGA development workflows
Technical fluency in GUI/IDE frameworks, design data models, and toolchain integration
Familiarity with hardware/software co-design and FPGA-based acceleration
Experience with or strong interest in AI/ML acceleration on FPGA platforms
Understanding of agentic AI, LLM copilots, and developer-facing AI tools
Familiarity with platforms like GitHub Copilot, Cursor, Windsurf, or equivalent
Ability to translate innovation into usable, production-ready tools
Strong communicator and cross-functional collaborator
Capable of influencing senior stakeholders and aligning teams toward a shared vision
Committed to mentorship, diversity, and building a healthy engineering culture

Responsibilities

Drive the Future of Agentic, AI-Powered Design
Lead the transformation toward intelligent and contextual development environments, powered by the latest in AI/LLM technology.
Define the vision for AI-assisted design using LLMs and agentic workflows
Build IDE integrations and tooling copilots tailored for FPGA developers
Partner closely with product, UX, and AI platform teams to deliver seamless, intelligent experiences
Lead and Scale a World-Class EDA Tooling Team
Oversee the full-stack development of Quartus front-end tools, including: Design entrance (schematic/coding interfaces) GUI frameworks IP integration and reuse Timing analysis and debug environments Core infrastructure and design databases
Foster technical excellence, reliable execution, and high product quality.
Build a culture of innovation and ownership across the team.
Enable AI Acceleration Through Smarter FPGA Development
Collaborate with architecture and hardware teams to ensure the front-end tooling supports AI acceleration use cases, including custom dataflow and ML model mapping
Drive integration of AI-specific IPs, reference designs, and optimization flows
Ensure the design environment is intuitive and scalable for engineers building AI/ML solutions on FPGAs