Senior Director, IO Analog Design Engineering

Intel • Chandler, AZ

7h • Hybrid

About The Position

The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is responsible for delivering industry defining analog and mixed signal IP for Intel's Client, Datacenter, AI and Foundry customers. The IO team owns high-speed serial IO and die-to-die interfaces across multiple advanced process nodes. As the senior engineering leader for this global organization, you will shape Intel's future of IO and chiplet interconnect technology. This leader will be responsible for the following: Setting and continuously refining a multi-generational roadmap for HSIO and D2D IP development, anticipating market and technology trends and architectural shifts and driving alignment across SoC, platform and product teams. Engaging directly with senior Intel architects and executives to define IP landing zones and build execution plans Driving IP development across architecture, logic, validation and analog design teams, while collaborating tightly with test chip, structural design and layout teams. Managing competing requirements, schedules, and resource balancing across multiple functional teams, including multi-site resource planning. Ensuring high quality and on-time IP delivery, including proactive risk management throughout the development lifecycle. Leading, growing and developing a high-performing global team of engineers across US and India, driving organizational clarity and alignment. Fostering a culture where issues surface and are addressed early. Driving efficiency throughout the development cycle, including the adoption of AI solutions across all job functions. Intel is building products that power the world and every silicon design has analog IP. This is an opportunity to shape the silicon products of the future and lead an incredible team of engineers.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Science, or a related field with 12+ years of experience
• Proven deep experience in analog IP development and delivering from concept to launch.
• 10+ years of proven success building, leading, and driving execution in silicon teams delivering to complex, high-impact programs

Nice To Haves

• 10+ years of experience leading analog IP design teams.
• Deep knowledge of high speed serial IO technologies such as PCIe/CXL and USB Type C and of die to die technologies such as UCIe.
• Demonstrated success managing global, multi-disciplinary engineering organizations.
• Experience navigating complex SOC customer negotiations.

Responsibilities

• Setting and continuously refining a multi-generational roadmap for HSIO and D2D IP development, anticipating market and technology trends and architectural shifts and driving alignment across SoC, platform and product teams.
• Engaging directly with senior Intel architects and executives to define IP landing zones and build execution plans
• Driving IP development across architecture, logic, validation and analog design teams, while collaborating tightly with test chip, structural design and layout teams.
• Managing competing requirements, schedules, and resource balancing across multiple functional teams, including multi-site resource planning.
• Ensuring high quality and on-time IP delivery, including proactive risk management throughout the development lifecycle.
• Leading, growing and developing a high-performing global team of engineers across US and India, driving organizational clarity and alignment.
• Fostering a culture where issues surface and are addressed early.
• Driving efficiency throughout the development cycle, including the adoption of AI solutions across all job functions.

Benefits

• We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
• Find out more about the benefits of working at Intel .

What This Job Offers

• Job Type: Full-time
• Career Level: Director