Senior Digital Verification Engineer

Silicon Labs•Austin, TX

6d•$126,000 - $234,000•Hybrid

About The Position

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com. Senior Digital Verification Engineer Austin, TX Meet the Team We are focused on producing world-class Wireless MCU products. The architecture specifications, design, verification, emulation, and implementation of the Wireless MCU SoCs are all the responsibilities of our team. The IPs on our chip include an embedded CPU system with analog and digital peripherals, advanced security, advanced power management, and best in class low power wireless modems. We strive to provide advanced technology solutions through innovation in custom RISC-V Cores and AI/ML accelerators. The position involves executing a verification plan on digital IP blocks using a combination of simulation and formal verification techniques. The qualified candidate should have built UVM test benches from scratch and taken them through all stages of execution. The candidate will interact with cross-functional teams to receive specs, create, and execute verification plans, and debug IP and system-level issues. Based on the project needs, the candidate will debug chip level tests for functionality, power, and performance.

Requirements

5+ years of design experience
Bachelor's or Master's degree in Electrical/Computer Engineering
Strong knowledge of Verilog, SystemVerilog, UVM, and C/C++
Knowledge of digital design, ARM, or RISC-V architecture and bus protocols
Knowledge of scripting languages like Perl, Python, Tcl, and shell
Advanced verification skill in SVAs, constrained random stimulus, and coverage analysis
C-based testcase development and debugging skills
Experience with artificial intelligence (AI) powered tools and technologies used to enhance productivity, analysis, and decision-making

Nice To Haves

Mixed Signal verification with RNM and SPICE models
DSP, digital wireless, modulation schemes, FEC
Verification and debug of low-power design with UPF
Technical leadership and mentoring experience.
Good written and oral communication skills.

Responsibilities

Block and IP Verification Create and execute the test plan with emphasis on metrics driven verification Constrained random tests, scoreboard, and coverage development Validate block power and performance requirements Apply formal verification tools like lint, auto, and property checks
System Level Verification Debug functional failures at subsystem and SoC levels Perform gate-level verification across corners and provide activity files for power analysis
Flows and Methodology Architect and implement Verification Components using UVM-based methods Develop verification flows and methodologies to enhance IP, SoC, and Formal Verification

Benefits

Great medical (Choice of PPO or Consumer Driven Health Plan with HSA), dental and vision plans
Highly competitive salary
401k plan with match and Roth plan option
Equity rewards (RSUs)
Employee Stock Purchase Plan (ESPP)
Life/AD&D and disability coverage
Flexible spending accounts
Adoption assistance
Back-Up childcare
Additional benefit options (Commuter benefits, Legal benefits, Pet insurance)
Flexible PTO schedule
3 paid volunteer days per year
Charitable contribution match
Tuition reimbursement
Free downtown parking
Onsite gym
Monthly wellness offerings
Free snacks
Monthly company updates with our CEO