Digital Design & Verification Engineer (Contractor)

Claros • Torrance, CA

1d • $80 - $100 • Hybrid

About The Position

Claros is a power management solutions company that is innovating at the intersection of power and compute to make AI more sustainable and widely available. By driving down the cost and complexity of power delivery and leveraging innovative hardware and software, the company seeks to decrease energy consumption, optimize power delivery, increase compute performance, and maximize the efficiency of AI operations.
We are seeking a motivated and detail-oriented Design & Verification Engineer to join our team in the development of digitally controlled power management integrated circuits (PMICs). The ideal candidate will have a strong foundation in ASIC design methodologies, with hands-on experience in timing closure, design optimization, and functional verification. This role spans the full lifecycle of PMIC digital design from RTL development and simulation through post-silicon validation using FPGA platforms.

Requirements

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• Experience with RTL coding using SystemVerilog
• Experience developing SystemVerilog testbenches with targeted and/or constrained-random test cases for functional verification.
• Familiarity & experience in leveraging simulation and verification features
• Assertions, Linting, Threading
• Metric Driven Verification (Code, Conditional Branch, Toggle, FSM Branch, Functional, etc.)
• Experience debugging hardware in a lab environment using benchtop equipment: oscilloscopes, waveform generators, power supplies, logic analyzers
• Solid understanding of ASIC design flows including RTL design, synthesis, timing closure, and verification.
• Experience with digital simulation tools (e.g., Xcelium, Questa, Vivado Simulator).
• Experience with FPGA development using Xilinx tools (Vivado, ISE) for prototyping and silicon validation.
• Proficient in scripting (Python, TCL, Perl) for automation and test.
• Strong digital design fundamentals and hardware debugging skills.
• Proficient with versioning software (Git)
• Excellent analytical and debugging skills
• Effective communication and documentation habits
• Proactive, detail-oriented, and committed to high-quality work
• Comfortable working in cross-functional teams and fast-paced environments

Nice To Haves

• Experience with post-silicon validation and debug of PMICs or mixed-signal ICs.
• Familiarity with standard cell libraries and digital integration in mixed-signal environments.
• Knowledge of digital control systems for power regulation, sequencing, or monitoring.
• Familiarity with Cadence digital implementation tools (Genus, Innovus, Conformal).
• Experience in hardware/software co-design and test automation.

Responsibilities

• Design and implement digital blocks within PMICs using Verilog/SystemVerilog and standard ASIC design flows.
• Participate in pre-silicon simulation and verification using Cadence tools and standard cell libraries.
• Support ASIC tape-out activities, including synthesis, static timing analysis, and design signoff.
• After silicon returns from the foundry, focus on developing FPGA-based test builds (using Xilinx tools) to validate and characterize fabricated PMIC silicon.
• Interface and integrate digital control logic with analog/mixed-signal blocks commonly found in power management applications.
• Write and maintain automation scripts for regression testing, build flows, and hardware validation.
• Collaborate with cross-functional teams including analog designers, layout, validation, and test engineers to ensure robust and reliable PMIC design.

What This Job Offers

• Career Level: Mid Level