Senior Digital Verification Engineer - Digital Beamforming Systems - TeraWave

BLUE ORIGIN • Los Angeles, CA

2d

About The Position

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! This role is part of TeraWave, a satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This network will service tens of thousands of enterprise, data center, and government users who require reliable connectivity for critical operations. As a Senior Digital Verification Engineer at Blue Origin, you will ensure the functional correctness and reliability of our mission-critical beamforming ASICs and FPGA designs. You will be a foundational member of the digital design team, responsible for developing comprehensive verification strategies and testbenches that validate complex DSP algorithms and digital communication systems before they fly on spacecraft. This role is ideal for an engineer who thrives on finding bugs, thinking adversarially about design, and building robust verification environments. You will work closely with DSP architects and digital designers to verify everything from individual signal processing blocks to complete system-level integration. Your work will directly impact the success and safety of Blue Origin's space communication systems.

Requirements

• B.S. in Electrical Engineering, Computer Engineering, or related field with 5+ years of experience in digital verification
• Strong expertise in System Verilog and verification methodologies (UVM, OVM, or VMM)
• Experience verifying complex digital designs (DSP, communications, or high-speed interfaces)
• Proficiency with industry-standard simulation tools (ModelSim, VCS, Xcelium, or Questa)
• Understanding of functional coverage, code coverage, and assertion-based verification
• Experience debugging RTL simulations and tracking down complex bugs
• Familiarity with scripting languages (Python, Perl, TCL) for test automation

Nice To Haves

• M.S. in a related field
• Experience with formal verification tools (Jasper, OneSpin, VC Formal)
• Knowledge of FPGA verification flows and hardware-in-the-loop testing
• Experience with high-level synthesis (HLS) verification
• Understanding of DSP algorithms and fixed-point arithmetic verification challenges
• Familiarity with ASIC verification flows, including gate-level simulation and SDF back-annotation
• Experience with FPGA emulation and acceleration platforms
• Background in communications systems or phased array verification

Responsibilities

• Develop and execute comprehensive verification plans for FPGA and ASIC designs implementing beamforming, SDR, and digital communication systems
• Create advanced testbenches using System Verilog and UVM (Universal Verification Methodology)
• Design constrained-random stimulus generators and self-checking verification environments
• Develop functional coverage models to ensure completeness of verification
• Create bus functional models (BFMs) and verification IP for standard and custom interfaces
• Implement assertion-based verification using SVA (System Verilog Assertions)
• Debug complex RTL/gate-level simulation failures and work with designers to resolve issues
• Develop co-simulation frameworks linking MATLAB/Python models with RTL simulations
• Support formal verification efforts for critical control logic and safety-critical blocks
• Create and maintain regression test suites and continuous integration flows
• Participate in design reviews, identifying potential verification challenges early

Benefits

• Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.
• Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level