Senior DFT Timing Signoff Engineer (STA)

Intel • Folsom, CA

11d • Hybrid

About The Position

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful. The Role: We are seeking a highly skilled and hands-on DFT/STA Engineer to join our full-chip timing organization supporting next-generation AI processors. This is a backend role focused on PrimeTime-based DFT-mode timing constraints, constraints hygiene, and signoff readiness. The role requires deep understanding of Tessent DFT architecture and implementation concepts-including Streaming Scan Network (SSN), IJTAG/test access integration (HTAP, TAPLink), and memory test/repair (MBIST/BISR)-and the ability to translate DFT intent into correct, auditable timing constraints and stable signoff across all DFT modes. You will collaborate closely with DFT architecture/implementation teams, RTL, Physical Design (Synthesis/CTS/PnR), and Product/Test Engineering to enable first-pass silicon success.

Requirements

• Bachelors & 8+ years or Masters & 6+ years in Electrical Engineering, Computer Engineering, or related field with 6+ years in the following:
• DFT and/or STA for complex SoCs with demonstrated ownership of PrimeTime-based signoff and constraints.
• Ownership of DFT-mode SDC development and PrimeTime STA signoff (PrimeTime-only signoff environment).
• Tessent DFT architecture concepts and integration flows, including Streaming Scan Network (SSN), IJTAG/test access integration (HTAP, TAPLink), and MBIST/BISR fundamentals.
• CDC/RDC fundamentals and their interaction with constraints, clocks, resets, and test modes.
• Verilog/SystemVerilog; ability to read/debug gate-level netlists and DFT-inserted structures.
• Tcl required; Python and/or shell strongly preferred.

Nice To Haves

• Hands-on Tessent flow experience (architecture-to-implementation), including SSN/IJTAG integration across hierarchical SoC/IP environments.
• Strong track record owning DFT-mode signoff hygiene for Scan Shift / Slow Capture and MBIST/JTAG across large MMMC environments.
• Experience with signoff guardrails and quality checks (lint, CDC/RDC, LEC, Spyglass DFT or equivalents; low-power intent checks when applicable).
• Proven ability to drive cross-team closure with PD and DFT stakeholders under aggressive schedules.

Responsibilities

• DFT Timing Constraints and PrimeTime Signoff Ownership Own the definition, generation, validation, and maintenance of comprehensive DFT timing constraints (SDC) in Synopsys PrimeTime for modes including Scan Shift, Scan Capture (slow/fast as applicable), JTAG/IJTAG, and Memory BIST.
• Own PrimeTime STA signoff for DFT modes at both block and top level across relevant corners and operating conditions; ensure correctness, coverage, and auditable exception governance (false paths, multicycle paths, case analysis).
• Establish and enforce constraints hygiene standards: mode separation, exception audits, constraint reviews/linting, and regression strategies to prevent drift and late-cycle surprises.
• Tessent DFT Architecture Collaboration (SSN / IJTAG / HTAP / TAPLink / MBIST) Partner with DFT architecture and implementation teams to support Tessent-based integration, including Streaming Scan Network (SSN) architecture/implementation considerations, IJTAG/test access strategy (HTAP, TAPLink), and MBIST/BISR collateral and constraints needs.
• Translate DFT architecture intent into timing assumptions and constraints that are signoff-safe, traceable, and robust across integration drops.
• Debug complex DFT insertion/integration issues (RTL and gate-level netlists) that impact test-mode timing closure and signoff.
• Backend Closure Execution (PD/CTS/ECO) Drive DFT-mode timing convergence by partnering with Synthesis/CTS/PnR teams to debug complex violations and guide/implement ECO strategies when needed.
• Develop repeatable signoff checklists and reporting that clearly communicate DFT-mode signoff readiness and risks to stakeholders.
• Flow Improvement and Automation Improve DFT/STA flows through automation (Tcl required; Python/shell preferred): multi-mode runs, report triage, regression checks, and signoff dashboards.
• Identify and implement methodology improvements that increase efficiency, reduce churn, and improve confidence in DFT-mode signoff.

Benefits

• We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
• Find out more about the benefits of working at Intel .

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees