Senior DFT Engineer

ARM • San Diego, CA

8d

About The Position

Arm's Solutions group DFT team implements DFT for SOC for client, datacenter, automotive, and IOT line of business using the latest DFT and process technologies. We closely collaborate with Arm's partners and internal RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE. We are currently hiring across three locations : San Jose , Austin , and San Diego .

Requirements

• This role is for a Senior DFT Engineer with 7+ years of proven experience in Design for Test
• Core DFT skills considered crucial for this position should include some of the following: Siemens DFT tools, Streaming Scan Network (SSN), Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics.
• Experience coding Verilog RTL, TCL and/or Perl
• Ability to work both collaboratively on a team and independently.
• Innovative and a passion for progress
• Hard-working and excellent time management skills with an ability to multi-task
• An upbeat approach to working on exciting projects on the cutting edge of technology!

Nice To Haves

• Familiarity with SoC style architectures including multi-clock domain and low power design practices.
• Familiarity with Arm IP like the following: Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug
• Background in high performance design, implementation and DFT timing constraints is a huge plus.
• Experience in datacenter chips is plus!
• Experience with 2.5D and 3D test

Responsibilities

• Implement innovative DFT logic into SoC as well as sub-system level and validate all DFT features using industry standard simulation tools.
• Verify DFT logic in RTL and gate level simulations.
• Generate ATPG patterns and debug coverage issues to meet target
• Collaborate with multi-functional teams to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static-timing-analysis and timing closure.
• Participate in ATE targeted test patterns generation, validation and silicon- debug activities
• Collaborate with Test and product engineering teams on silicon characterization and validation.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: No Education Listed
• Number of Employees: 5,001-10,000 employees