Senior Design Verification Engineer

Altera • San Jose, CA

2d

About The Position

Altera is seeking a Senior Design Verification Engineer to drive verification of complex FPGA and SoC designs from architecture through silicon validation. This role is a highly technical, hands-on position for an experienced verification engineer who will own verification strategy for major blocks or full subsystems, influence design quality, and serve as a technical leader within the verification community.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with the 15+ years of experience in the following:
• 15+ years of Design Verification experience in complex ASIC, SoC, or FPGA environments
• Strong expertise in SystemVerilog, UVM, constrained-random verification, and functional coverage
• Proven experience verifying large-scale digital designs and IPs
• Solid understanding of digital design, microarchitecture, and system-level integration
• Experience debugging complex functional and performance issues in RTL designs
• Applicants must be eligible for any required U.S. export authorizations.

Nice To Haves

• Master’s degree or PhD in Electrical Engineering, Computer Engineering, or a related field
• Experience with formal verification, emulation, and acceleration platforms
• Background in FPGA or SoC FPGA architectures
• Familiarity with power-aware verification and low-power methodologies
• Experience developing reusable verification IP and frameworks
• Demonstrated ability to influence technical direction without formal people management

Responsibilities

• Own and execute design verification for complex FPGA and SoC blocks and subsystems
• Develop verification plans, testbenches, checkers, and coverage models
• Drive verification methodology using SystemVerilog, UVM, constrained-random testing, and assertions
• Analyze functional coverage, identify verification gaps, and ensure thorough sign-off
• Collaborate closely with Design, Architecture, and Emulation teams to influence microarchitecture and design quality
• Debug complex RTL and system-level issues across simulation, emulation, and post-silicon environments
• Contribute to verification infrastructure, automation, and reusable VIP development
• Mentor junior verification engineers through technical guidance and code reviews
• Support silicon bring-up and correlation between pre-silicon and post-silicon results

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level