Senior Design Verification Engineer

Microsoft•Raleigh, NC

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for a Senior Design Verification Engineer to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Artificial Intelligence System on Chip (AISoC) Silicon team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for a Senior Design Verification Engineer with a passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Senior Design Verification Engineer to join the team.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Nice To Haves

7+ years of technical engineering experience
OR Bachelor's degree in Electrical Engineering, Computer Engineering, or related field AND 5+ years of technical engineering experience
OR Master's degree in Electrical Engineering, Computer Engineering, or related field AND 3+ years of technical engineering experience
OR Doctorate degree in Electrical Engineering, Computer Engineering, or related field
In depth knowledge of verification principles, testbenches, stimulus generation, and UVM based test environments.
Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments.
Experience with verification for product from definition to Silicon, including writing test plans, developing tests, debugging failures and coverage signoff in C/C++ and Universal Verification Methodology (UVM).
Scripting language such as Python or Perl or shell scripts.
10+ years of design verification experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamental.
Verification experience for an IP or SS or SOC related to CPUs, VPUs, GPUs, Tensor unit, or similar.
Knowledge of System Verilog class, constraints, coverage and assertions.
Experience in scripting languages such as Python or Perl.
Hands-on experience in Formal property verification, formal verification of computational data path designs.

Responsibilities

Perform pre-silicon verification for complex IP, including creating testplans, developing Universal Verification Methodology (UVM) components and environments from scratch, writing test cases, debugging failures to root cause issues, running and maintaining regression suites, and closing coverage.
Interact with architects and design engineers to create testplans covering verification strategy, test requirements, and test environments for IP/SS/SOC level verification.
Define verification strategy, requirements, test environments for IP/SS/SOC level verification.
Create test-plans and write tests to provide complete features coverage.
Develop and implement technical solutions to complex quality and design challenges.
Develop verification components like scoreboards, sequences, constraints, assertions and functional coverage.
Triage and debug testbench, simulation, and emulation fails.
Develop Makefiles and scripts for verification infrastructure.
Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment.
Collaborate with teams across sites and geographies.