Senior Design Automation Engineer

Altera Semiconductor•San Jose, CA

About The Position

About Altera At Altera™, our independence as the world’s largest pure ‑ play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry ‑ leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry. About the Role Altera is seeking a Senior Design Automation Engineer to join our Design Methodology Automation and Infrastructure Team. The Design Methodology Automation and Infrastructure Team is responsible for building and maintaining the core automation infrastructure that supports Altera’s FPGA design flows—from RTL to GDSII. In this senior role, you will drive the architecture, development, and optimization of highly automated, reliable, and scalable flow systems that enhance design productivity and accelerate development cycles for next-generation FPGA products. You will influence technical direction, mentor junior engineers, and collaborate closely with cross-functional teams to deliver world-class automation solutions.

Requirements

Bachelor's or Master's in Computer Science, Electrical Engineering, or equivalent, with a minimum of 8+ years of experience in IC Design or Design Automation and experience in the following:
Extensive experience with industry-standard EDA tools and hands-on expertise in design methodologies across multiple domains, such as Front-End Logic Design flows, Design Intent and FPGA-specific flows, Design Verification flows, and Design-for-Test (DFT) flows (with Back-End flow knowledge considered a plus).
Strong programming skills in Python, Tcl, C-shell, C, C++, or similar languages.
Familiarity with ML/AI applications and algorithms and their use in EDA or design methodology optimizations.
Proven leadership skills for driving collaborative, cross-functional projects, with strong communication and influencing abilities

Responsibilities

Architect next-generation unified FPGA/SoC design methodologies spanning Front-End, handoff to Backend, Design Verification, Design-For-Test (DFT), Design Data Management/Release flows, and FPGA-specific flows such as Design Intent and Configuration Management.
Develop and integrate state-of-the-art EDA solutions, including ML/AI-enhanced tools, flows, and methodologies—sourced externally or developed internally—to create sustainable, scalable automation solutions for multiple chip design programs.
Collaborate with design automation technical leads, design domain leads, and domain managers to define and drive new design automation architectures from concept through full production deployment across upcoming product programs.
Partner with EDA vendors to evaluate, explore, and extend tool capabilities that improve design quality, shorten turn-around time, and enhance design optimization.
Architect, develop, deploy, and maintain advanced design automation flows and methodologies for digital and/or analog design at scale.
Lead evaluation, integration, and enhancement of EDA tools, driving improvements in design productivity, efficiency, and quality across multiple design teams.
Design and implement robust automation frameworks that reduce manual effort, increase reproducibility, and improve overall design throughput.
Identify workflow bottlenecks across design, verification, CAD, and methodology teams and lead cross-functional initiatives to streamline FPGA design execution.
Provide deep technical expertise in scripting, tool customization, and flow development for advanced semiconductor design needs.
Drive continuous innovation in design automation infrastructure through adoption of new methodologies, technologies, and optimizations.
Collaborate with internal and external EDA vendors, owning issue resolution, feature requests, and deployment of next-generation capabilities.
Mentor and provide technical leadership to junior engineers within the Design Automation organization.