Senior ASIC Verification Engineer

NVIDIA•Austin, CA

About The Position

We are looking to hire a Chip Design Verification Engineer to join NVIDIA Chip Design group. The work environment is versatile, educational, dynamic and challenging as our employees are currently working on innovative, next-generation networking devices at the forefront of technology in terms of performance and power efficiency. Our team is at the heart of this challenge, verifying the industry-leading, high-performance network switching ASICs that form the backbone of the world's most advanced AI data centers. We are seeking a senior verification engineer to help us ensure the quality and correctness of this critical technology. What you will be doing: Work in a combined design and verification team which develops core units within the Networking silicon. Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements. Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation. Lead the verification effort for core switching fabrics, packet buffering architectures, and traffic management subsystems, ensuring functional correctness and performance at scale.

Requirements

B.SC./ M.SC. in Computer Engineering /Electrical Engineering/Communication Engineering or equivalent experience
8+ years of proven experience in Design Verification.
Proven, hands-on experience verifying sophisticated network switching ASICs, with deep knowledge of core switching logic and advanced buffering architectures
Demonstrated ability to own verification strategy and execution from the block-level through full-chip (SoC) integration.
Sharp analytical and debugging skills with a track record of root-causing complex hardware, testbench, or software-driven issues.
Excellent organizational and communication skills, with the ability to manage priorities and negotiate solutions across design, verification, and architecture teams.

Nice To Haves

Deep experience verifying advanced traffic management (TM) and Quality of Service (QoS) features, such as complex schedulers, shapers, and congestion control mechanisms
Proven experience building performance-focused verification environments to measure and stress test latency, throughput, and fairness
Knowledge in SimVision and Xcelium

Responsibilities

Work in a combined design and verification team which develops core units within the Networking silicon.
Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.
Lead the verification effort for core switching fabrics, packet buffering architectures, and traffic management subsystems, ensuring functional correctness and performance at scale.