Senior ASIC Verification Engineer

NVIDIA•Durham, NC

23h

About The Position

We are now looking for a Senior Verification Engineer for our Memory Management Unit. NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world’s leading GPUs. This position offers the opportunity to have a real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. What you’ll be doing: As a senior member of our verification team, you'll understand the design & implementation with focus on Memory Management unit, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), implement test/coverage plans, and verify the correctness of the design. Collaborate with architects, designers, software engineers across sites to accomplish your goals. Plan and work on strategic direction of the methodology for the testbench with advance methodology.

Requirements

Bachelors or Masters Degree in Electrical Engineering or Computer Science or Computer Engineering or equivalent experience
5+ years of relevant work or research experience
Exposure to Computer Architecture, ASIC design and verification methodology is required
Strong ability with SystemVerilog, C and/or C++, test planning, coverage closure, and creating reusable verification components.
Knowledgeable in constrained random testing with functional coverage and assertion-based verification.
Understanding of object oriented programming concepts.
Exposure to simulation tools like VCS, IES and debug tools like Debussy, GDB.
Strong interpersonal skills.
Good debugging and problem solving skills.

Nice To Haves

Understanding of memory subsystem micro-architecture, cache topologies and policies, memory management, interconnects, and/or arbiter designs is a huge plus.
Experience with Universal Verification Methodology (UVM), SystemVerilog checkers and scoreboards.
Assertion-based verification, Semiformal Verification (SFV).
Perl or Python knowledge.

Responsibilities

Understand the design & implementation with focus on Memory Management unit
Define the verification scope
Develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors)
Implement test/coverage plans
Verify the correctness of the design
Collaborate with architects, designers, software engineers across sites to accomplish your goals
Plan and work on strategic direction of the methodology for the testbench with advance methodology