Senior ASIC Timing Engineer

NVIDIA•Austin, CA

About The Position

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of something great, join us today! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing! More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to tackle, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence.

Requirements

BS (or equivalent experience) in Electrical or Computer Engineering with 5 years experience or MS (or equivalent experience) with 2 years’ experience in Timing and STA
Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation and management.
Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis.
Expertise in physical design and optimization e.g., placement, routing, logic restructuring, etc. to improve timing and power.
Expertise and in-depth knowledge of industry standard STA and timing convergence tools.
Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes.

Nice To Haves

Background in domain specific STA and timing convergence, such as GPUs, CPUs, DPUs/Network processors, or SOCs
Background in logic synthesis and equivalence checking/FV.
Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, BIST, etc.
Understanding and timing closure of digital logic/macros in AMS designs/IPs.
Experience in methodology and/or flow development as well as automation.

Responsibilities

Drive Timing Analysis and Closure: Lead the timing analysis and closure processes for Nvidia’s GPUs, CPUs, DPUs, and SoCs at block level, cluster level, and full chip level.
Collaborate with Cross-Functional Teams: Work closely with RTL, DFX, Clocks, and other teams to devise timing closure strategies, create timing constraints, and drive timing and power convergence as well as implement ECOs.
Contribute to Cutting-Edge Projects: Play a pivotal role in the success of our innovative projects and advancement of our technology. Leverage your expertise to improve timing convergence flows in collaboration with methodology teams.