Senior ASIC Timing Engineer

NVIDIA • Durham, NC

1d

About The Position

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a meaningful, growing and professional environment where you make a significant impact in a technology-focused company.

Requirements

• Great teammate
• BS (or equivalent experience) in Electrical or Computer Engineering with 8 years experience or MS with 4+ years experience in Synthesis and Timing.
• Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.
• Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis.
• Expertise in physical design and optimization e.g., placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power, along with a background in implementing them through ECOs.
• Background in logic synthesis and/or logical equivalence checking (LEC).
• Expertise and in-depth knowledge of industry standard EDA tools (Synopsys PrimeTime or Cadence Tempus).
• Proficiency in Python, Tcl and Make for automation and scripting tasks.

Nice To Haves

• Background in domain specific STA and timing convergence, such as CPUs, GPUs or Network processor implementation or SOCs.
• Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan shift and capture, transition faults, BIST, etc.
• Knowledge of deep sub-micron technology and associated process variations effects, including modeling and converging considering process variations.
• Experience in methodology and/or flow development as well as automation.

Responsibilities

• Drive physical design and timing of high-frequency and low-power DPUs and SoCs at block level, chiplet level, and/or full chip level.
• Analyze and optimize design constraints and synthesis parameters to achieve performance, power, and area targets.
• Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees