Senior ASIC Design Engineer

Chelsea Search Group•Minneapolis, MN

9h•Hybrid

About The Position

As ASIC Design Lead, you will play a pivotal role in the development of custom-designed ASICs. Your expertise will span the entire chip design lifecycle, from conceptualization to implementation. You’ll collaborate with cross-functional teams, ensuring successful chip development while adhering to performance, power, and area targets. The right candidate will be someone with high aptitude who is currently hands on designing complex digital blocks, with strong knowledge/experience across the complete ASIC/SOC design flow. The ideal candidate will additionally have experience with radiation-hardened design, analog/mixed-signal design and EDA, and PCIE or DDR development. Additional duties include the evaluation of customer requirements and estimates of effort/expenses for potential new business, and participation in identifying problems with and improvements to, internal design methodologies.

Requirements

Bachelors/Masters in Electrical Engineering/Computer Science or equivalent.
7+ years of direct industry experience with ASIC and/or SoC design.
Proficiency in Synopsys Design Compiler and other EDA tools.
Strong understanding of digital design principles.
Familiarity with RISC architectures (e.g., ARM, MIPS).
Excellent problem-solving skills and attention to detail.
A strong background in RTL based digital IC design using Verilog/SystemVerilog
Proven track record of first-pass successes.
A self-starter with the ability to assume leadership roles.
Ability to work well in a diverse team environment.
Willingness to Mentor newer senior engineers.
Experience with industry standard development tools and methodologies.
Understanding industry standard interfaces such as GB Ethernet, PCIe, and DDR4+.

Nice To Haves

experience with radiation-hardened design
analog/mixed-signal design and EDA
PCIE or DDR development

Responsibilities

Chip Architecture and Development: - Collaborate with system architects to define chip functionality, interfaces, and performance targets. - Develop detailed specifications for the chip’s components. - Use delivered vendor IP and integrate that design into the current architecture
RTL Design and Synthesis: - Use Synopsys Design Compiler to create RTL (Register Transfer Level) designs. - Optimize RTL code for area, power, and performance. - Implement and verify complex digital blocks.
Constraint Development: - Develop timing constraints for the entire chip. - Work closely with physical design teams to ensure successful place-and-route.
Physical Design Collaboration: - Collaborate with physical design teams on floor planning, placement, and routing. - Address any design closure issues.
Verification Support: - Work with verification engineers to ensure functional correctness. - Assist in creating testbenches and verifying the chip’s functionality.
Modern revision-control tools and best-practices in a collaborative, multi-site design community.
Proficiency with UNIX/Linux incl. shell scripting, text utilities (e.g. sed, awk, grep), using Modules, high-level programming such as C/C++, PERL/Python/TCL scripting.
Proficiency with Windows apps, incl. Word, Excel, PowerPoint, Visio, Project, PDF conversion.