Senior ASIC Design Verification Engineer

NVIDIA

23h • Hybrid

About The Position

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. NVIDIA is seeking best-in-class ASIC Verification Engineers to verify the design and implementation of the world’s leading inference accelerator. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people around the globe. Their mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will help to build the high-performance processor elements that implement programmable compute and graphics functionality.

Requirements

• Bachelors Degree in EE, CS or CE (or equivalent experience) and 8+ years of relevant industry experience
• Background with building block and SoC level testbench utilizing strong debugging and analytical skills
• Experience in verification using random stimulus along with functional coverage, assertion-based verification methodologies and tools
• Expertise in SystemVerilog and Universal Verification Methodology (UVM)
• Experience with design and verification tools (VCS, Verdi or equivalent)
• Knowledge of ASIC design flow, from specification to GDS

Nice To Haves

• Background in UPF power verification is a plus
• Experience in netlist and DFT verification is a plus
• Perl/Python and C/C++ programming language experience desirable
• Knowledge of applying machine learning to ASIC verification flow

Responsibilities

• Verify the design and implementation of inference accelerator
• Responsible for verification of the ASIC design, architecture, reference models and micro-architecture using advanced verification methodologies
• Understand the design and implementation of your unit, define the verification scope, develop the verification infrastructure and verify the correctness of the design
• Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks
• Implement and optimize automated verification flows to improve productivity and efficiency
• Stay updated on the latest trends and advancements in ASIC design verification and incorporate innovative techniques into the verification process

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level