Semiconductor Packaging Engineer (Intern 2026)

Astera Labs Early Career • San Jose, CA

2d

About The Position

As an Astera Labs Semiconductor Packaging Intern , you will be part of the packaging team that develops Astera Labs’ portfolio of connectivity products in the world’s leading cloud service providers and server and networking OEMs. You will work to enhance the key areas of package development cycles such as package design, modeling, automation flow, and documentation. You will also work cross-functionally to understand project requirements and develop solutions.

Requirements

• Working towards M.S. or PhD in Electrical Engineering or related field
• Cumulative 3.3/4.0 GPA, or higher
• Entrepreneurial, open-minded behavior and hands-on work ethic with the ability to prioritize a dynamic list of multiple tasks.
• Working with minimal supervision to deliver solutions in a fast-paced environment.
• Strong time management skills and strong written and verbal communication skills
• Coursework in RF/microwave, communication systems and signal analysis, semiconductor manufacturing, or circuit design.

Nice To Haves

• Understanding or coursework in signal and power integrity is a plus.
• Understanding or coursework in semiconductor packaging is a plus.
• Scripting or software development experience in popular programing languages such as Python, Visual Basic, or equivalent.
• Experience with physical design or layout tools such as AutoCAD or Cadence Allegro is a plus.
• Experience of using 3D Electromagnetic simulation tools such as ANSYS is a plus.
• Knowledge of semiconductor multi-layer flip-chip package (FCBGA/FCCSP) is a plus.

Responsibilities

• Support package design, modeling, automation, and documentation for Astera Labs’ connectivity products.
• Collaborate cross-functionally to understand requirements and develop solutions throughout the packaging development cycle.

What This Job Offers

• Career Level: Intern
• Number of Employees: 251-500 employees