RTL Design Engineer

Broadcom•Irvine, CA

About The Position

Broadcom’s Central Engineering Group is seeking a candidate to lead the digital design and verification of a broad range of analog mixed signal IP and IOs, including leading-edge AI programs on advanced nodes. Joining a world-class team of engineers with a highly collaborative culture, the role offers opportunities for growth and development. Define the digital architecture and verification strategies for complex AMS and IO subsytems Design, synthesis, and verification of Verilog/SystemVerilog RTL. Analysis, debug, and resolution of Lint and CDC issues in the design. Design convergence to timing closure utilizing RTL optimization strategies. Conduct formal verification of design with Synopsys Formality / Cadence Conformal. Generate timing constraints for Synthesis and STA at the block-level and SoC top-level. Drive comprehensive test plans to ensure quality of design. Collaborate with cross-functional teams, ranging from analog/mixed-signal circuit designers to SoC-level system integration. Create and maintain detailed specification, design, and verification documentation.

Requirements

MS +10 years of relevant industry experience.
Experience with digital implementation flow from RTL synthesis to timing closure.
Deep understanding of timing analysis with Primetime flow and generation of Liberty models.
Experience with Tessent tool for DFT insertion and verification
Proficient with Perl, Python and Tcl scripting.
Strong problem solving skills with attention to detail.
Must be self-motivated and able to work effectively across internal and external engineering teams.

Nice To Haves

Solid understanding of transistor-level circuit behavior.
Familiar with Cadence Schematic/Layout, SPICE/Spectre circuit simulation.
Experience with advanced FinFET process nodes , including features, technology limitations and PPA tradeoffs.

Responsibilities

Define the digital architecture and verification strategies for complex AMS and IO subsytems
Design, synthesis, and verification of Verilog/SystemVerilog RTL.
Analysis, debug, and resolution of Lint and CDC issues in the design.
Design convergence to timing closure utilizing RTL optimization strategies.
Conduct formal verification of design with Synopsys Formality / Cadence Conformal.
Generate timing constraints for Synthesis and STA at the block-level and SoC top-level.
Drive comprehensive test plans to ensure quality of design.
Collaborate with cross-functional teams, ranging from analog/mixed-signal circuit designers to SoC-level system integration.
Create and maintain detailed specification, design, and verification documentation.