RTL Design Engineer - Early Career

Marvell Technology•Westborough, MA

1d•Onsite

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Infrastructure Processor Business Unit, a part of Networking and Processor Business Group, encompasses OCTEON and the award-winning OCTEON Fusion-M® product families. The SoC family of multi-core CPU processors and Radio Access SoCs offer best-in-class performance, low power, rich software ecosystem, virtualization features, and open source application support with highly optimized custom ARM CPU cores providing an excellent solution for a highly flexible end-to-end optimized 5G platform. As part of the Infrastructure Processor unit at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers’ specifications whether they’re a major telecom organization or automotive company, etc. What You Can Expect In this in-office role in Westborough, MA, you’ll work day-to-day to develop and optimize RTL for performance, power, and area for assigned blocks, all for the next generation of cloud, networking, and security processors

Requirements

Bachelor’s Degree in Electrical Engineering or Computer Engineering with 1-2 years of related professional experience OR a Master’s Degree in Electrical Engineering or Computer Engineering
Your coursework must have included some analog classes, Verilog or VHDL, basic circuits, and computer architecture
You have used a tool like Synopsys, Cadence, or Mentor to run simulations
Be comfortable working in a Linux environment and doing scripting with Python
Be extremely detail-oriented and ready to iterate a design again until it is refined completely
Work and communicate well with your team, keeping them in the loop about your progress, issues you encounter

Responsibilities

Develop scalable and maintainable design components, and reusable infrastructure logic
Collaborate with architecture, verification team members, drive design reviews
Participate in detailed design and micro‑architecture reviews, contributing to continuous improvement of design, verification, and methodology flows