RTL Arm Coresight Lead Engineer

Quest Global•Sunnyvale, CA

52d•$40,000 - $50,000

About The Position

Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies and industries, alongside the contributions of diverse individuals and their areas of expertise, we are able to solve problems better, faster. This multi-dimensional approach enables us to solve the most critical and large-scale challenges across the aerospace & defense, automotive, energy, hi-tech, healthcare, medical devices, rail and semiconductor industries. We are looking for humble geniuses, who believe that engineering has the potential to make the impossible possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers. As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we're eager to hear from you. The achievers and courageous challenge-crushers we seek, have the following characteristics and skills

Requirements

System-on-Chip (SoC) Design: Solid understanding of SoC architecture and design principles, especially for ARM-based systems.
ARM Technology: Familiarity with ARM cores and the CoreSight debug architecture.
AMBA/AXI Bus Architecture: Experience with on-chip bus protocols, especially AMBA/AXI, which are foundational for CoreSight integration.
ASIC Design Flow: Knowledge of ASIC design and prototyping flows, including integration and testing for complex systems.
EDA Tools & Simulators: Proficiency with Electronic Design Automation (EDA) tools and ISA simulators.
Debug & Trace Infrastructure: Understanding of CoreSight components such as Debug Access Port (DAP), APB Interconnect, Embedded Cross Trigger, Trace Macrocells (ETM, STM, ITM), Trace Funnels, Replicators, and Trace Sinks (TPIU, ETB, ETF).
Integration of Debug Features: Ability to integrate and validate debug and trace features across multiple CPU and DSP cores within the SoC.
System Discovery & Programmer's Model: Familiarity with system-level discovery and programming models for CoreSight.
Clocks, Reset, and Power Management: Knowledge of how debug and trace features interact with system clocks, resets, and power domains.

Responsibilities

Integrate ARM Coresight debug and trace components into SOC designs, following established architecture and integration guidelines to ensure reliable system visibility and debug capabilities.
Develop, implement, and maintain SDC (Synopsys Design Constraints) for timing closure across SOC blocks, collaborating with physical design teams to align constraints with floorplan, clocks, and interfaces.
Work closely with architecture, verification, and software teams to clarify Coresight requirements, integrate IPs, and support feature enablement and basic tooling workflows.
Debug Coresight integration issues such as connectivity, trace capture, and protocol mismatches, contributing to root-cause analysis and documenting solutions.