Principal Verification Engineer

Rambus • San Jose, CA

14d • Hybrid

About The Position

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Verification Engineer to join our Memory Interconnect Design team. You will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. Are you a seasoned Verification Engineer ready to make a real impact? Join Rambus in this high-visibility role where you’ll lead the charge in defining and executing Verification Strategies across multiple product lines and global sites. This is your chance to take full ownership, collaborate with top-tier design teams, and shape the future of cutting-edge technology! Enjoy the best of both worlds with our hybrid role, working alongside top talent in cutting-edge facilities while enjoying the vibrant lifestyle each city offers! Whether it’s the innovation and energy of Silicon Valley (San Jose, CA) or near the Santa Monica mountains in scenic Agoura Hills, CA. You can also be in the thriving Tech Suburb in Johns Creek, GA just outside of Atlanta to the renowned Research Triangle Park in Morrisville, North Carolina.

Requirements

• MSEE & 10+ years or PhD EE & 7+ years’ experience of Verification
• Significant Experience with coding in System Verilog or Verilog and UVM methodology
• Significant Experience with standard ASIC Verification flow/software tools
• Simulation tools: Synopsys VCS, Cadence Xcelium
• Verification Methodologies: UVM (Universal Verification Methodology)
• Coverage & Analysis: Cadence IMC (Incisive Metrics Center)
• Strong knowledge of scripting, Linux/Unix environment
• Experience in leading and driving technical solutions across organization
• Good written & verbal communication skills
• A strong commitment & ability to work in cross functional and globally dispersed teams

Nice To Haves

• Verification of DDR memory interfaces
• Experience working in Analog/Mixed-Signal Products
• Verification Methodologies : SVA (System/Verilog Assertions)
• Regression Management : Jenkins (CI/CD Integration)

Responsibilities

• Lead the charge on full-chip and block-level verification, ensuring our designs meet the highest standards.
• Collaborate closely with Architects, Logic, and Mixed-Signal Designers to define and execute robust verification plans.
• Build advanced test environments using UVM methodology, including testbenches, monitors, and scoreboards.
• Drive quality by achieving code coverage goals and delivering thoroughly verified silicon.
• Partner with Lab/System teams to develop test plans, support silicon bring-up, and debug real-world issues.
• Innovate within a dynamic R&D environment , contributing to the evolution of our verification flows and methodologies.
• Mentor and inspire junior engineers, helping to grow the next generation of technical talent.

Benefits

• Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program and gym membership.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Education Level: Ph.D. or professional degree
• Number of Employees: 501-1,000 employees