Principal Engineer - CAD (Physical Verification)

Microchip•Chandler, AZ

1d•$75,000 - $232,000

About The Position

The CAD group at Microchip offers global support for multiple technology nodes and tools used in product development providing innovative solutions for the design community. The candidate will focus on flow development and support for back end physical verification. If you have a solid software background and are interested in supporting semiconductor chip design, this maybe the job for you. Expertise using Siemens Calibre and/or Cadence Pegasus DRC, LVS and PERC tools is paramount. Candidate should not only know how to run the tools and debug results, but also have strengths in developing the verification run decks and in automating flow/procedures. An overall strong understanding in both the digital and analog sides of design is important to be effective, since development and support work will span a variety of design styles. Additionally, both circuit/electrical and layout/physical knowledge is important. The candidate will: Develop physical verification regression test cases to QA physical verification decks Support Layout and Design engineers with physical verification activities using verification tools such as Siemens Calibre, Cadence Pegasus, or Synopsys Hercules Utilize Knowledge of advanced EDA methods to support ESD, ERC, Voltage-Aware DRC, via doubling methodologies, etc. Work with Technology Development and Device Engineering to develop DRC rules, additional devices, and design for manufacturability checks Develop rule decks as needed to support flow Verify and enhance foundry rule decks Support remote sites worldwide with layout verification activities Support debug of physical verification issues Work as a member of team to develop flows to improve quality and reliability of devices The tasks this candidate will be assigned depends on their experience. There are several areas in which we are shorthanded. Potential task assignments would include: Building of regression test cases for several PDKs of various process technologies Supporting 4nm to 600nm PDKs from TSMC, Global Foundries, Vanguard, Dongbu, Magnachip, etc. Calibre/Pegasus PERC – several PDKs still require PERC setup.

Requirements

Bachelors with 10+ years developing and supporting physical verification activities, or Masters with 7.5+ years developing and supporting physical verification activities
In depth knowledge of Calibre DesignRev scripting
Fluent with SVRF and TVF
Accomplished at debugging PV issues with RVE, Vue or other EDA visualizer
Familiar with customizing Calibre Interactive
Skilled with Tcl/Tk, Perl, Python, and other programming languages, inside and outside of EDA tools
Solid knowledge of layout rules and concepts, device identification concepts, and foundry rules
Strong knowledge of Design for Manufacturing solutions affecting quality, reliability, and yield of designs
Excellent verbal and written communication and interpersonal skills

Nice To Haves

Prefer extensive knowledge of Calibre/Pegasus/Hercules syntax and semantics, or similar layout verification tool
Strong knowledge of Cadence Virtuoso and/or CalibreDRV
Prefer Extraction, Reliability and Dynamic Noise related knowledge

Responsibilities

Develop physical verification regression test cases to QA physical verification decks
Support Layout and Design engineers with physical verification activities using verification tools such as Siemens Calibre, Cadence Pegasus, or Synopsys Hercules
Utilize Knowledge of advanced EDA methods to support ESD, ERC, Voltage-Aware DRC, via doubling methodologies, etc.
Work with Technology Development and Device Engineering to develop DRC rules, additional devices, and design for manufacturability checks
Develop rule decks as needed to support flow
Verify and enhance foundry rule decks
Support remote sites worldwide with layout verification activities
Support debug of physical verification issues
Work as a member of team to develop flows to improve quality and reliability of devices
Building of regression test cases for several PDKs of various process technologies
Supporting 4nm to 600nm PDKs from TSMC, Global Foundries, Vanguard, Dongbu, Magnachip, etc.
Calibre/Pegasus PERC – several PDKs still require PERC setup.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments.
In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature.
Find more information about all our benefits at the link below:
Benefits of working at Microchip
The annual base salary range for this position, which could be performed in the US, is $75,000 - $232,000.
Range is dependent on numerous factors including job location, skills and experience.

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