Principal Silicon Engineer

Microsoft • Raleigh, NC

6h

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for a Principal Silicon Engineer to help achieve that mission.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the AISE team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for a Principal Silicon Engineer with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a Principal Silicon Engineer to join the team.

Requirements

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
• This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Nice To Haves

• Bachelor of Science in Electrical or Computer Engineering.
• 8+ years of experience in RTL design and design checks (CDC/RDC/VCLP/LINT).
• 8+ years of experience in Synthesis, Timing constraints and Power Performance Area (PPA) trade-offs.
• Proficiency in RTL to Physical Design collateral development including timing and synthesis constraints.
• Knowledge of full RTL2GDS flow.
• Hands-on experience with industry tools for synthesis, STA, and PD flows (e.g., PrimeTime, Genus/DC, Innovus/ICC2).
• Proficiency in recent synthesis tool capabilities and methods for QoR improvement.
• Proficiency in static timing analysis.
• Familiarity with RTL and gate-level power analysis/optimization, UPF, and power-intent verification.
• Experience with the project-level setup and configuration of 1 or more of the tools related to above disciplines.
• Proficiency in translating physical design results into feedback for flow or RTL improvement.
• Proficiency in Tcl, Python

Responsibilities

• Lead the capture and validation of design intent for digital and mixed-signal blocks, ensuring accurate constraints and seamless integration across front-end and physical design flows.
• Provide static timing leadership for mixed-signal interfaces, driving timing closure, exception quality, and correlation across corners.
• Partner closely with RTL, PD, mixed-signal, DFT, and CAD teams to resolve cross-domain issues and maintain alignment on timing, power, and functional requirements.
• Run, review and debug physical design flows, timing reports, ensuring consistency with synthesis and STA assumptions and driving convergence through targeted mitigations.
• Contribute to design automation including leveraging AI, constraint-checking, and flow improvements that enhance execution efficiency and PPA.
• Operate with limited direction, demonstrating strong ownership, attention to detail, and the ability to communicate clear, data-driven status, risks, and mitigation plans to program leadership.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: Ph.D. or professional degree