Principal Engineer, SOC Design
About The Position
The DRAM Development Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, HBM and NAND Flash. DDL’s vision is to solve key problems of Cloud & Data center by developing the new technology for memory and storage. The SOC team within DDL focuses on the development of silicon solutions. We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps. Come join the team that is creating new computing system architectures needed to support emerging machine learning applications, data analytics and edge computing. You’ll focus on enhancement of memory and storage capability by developing prototype and production controllers.
Requirements
- Bachelors in Electrical, Computer Science or related with 20+ years of experience or Masters in Electrical, Computer Science or related Science with 18+ years of Industry Experience or PhD in Electrical, Computer Science or related Science with 15+ years of Industry experience preferred.
- Highly motivated with good verbal and written communication skills.
- Hands on knowledge & experience in ASIC design flow from design to tape out.
- Experience & Good knowledge in ATE vector generation, testing and silicon bring up.
- Experience in the commercial IPs such as UCIe, CPU, Ethernet, and DDR interfaces.
- Good understanding of PPA (performance, power, and area) trade-offs.
- Experience in SoC level synthesis, timing analysis, lint check, CDC checks.
- Experience in interfacing 3rd party service companies for DFT/PI/PD.
- Good knowledge and experience in AMBA bus fabric, ARM cores.
- Self-motivated problem-solver with an ability to work well in a team.
- You’re inclusive, adapting your style to the situation and diverse global norms of our people.
- An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
- You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
- Innovative and creative, you proactively explore new ideas and adapt quickly to change.
Responsibilities
- Participate in architectural definitions and responsible for micro architecture of subsystem and/or chip level.
- Responsible for top integration, logic design and RTL implementation along with quality check (Assertion, Lint, CDC, and STA).
- Reviews 3rd party IPs including ARM cores, DDR controller, and UCIe PHY and
- Responsible for integrating the third part IPs and sub system at top level
- Work closely with architects and verification engineers to ensure sound design at SoC level.
- Work with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis
Benefits
- Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.
- Enjoy Time Away You’ll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.
- Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.
- Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you’ll have support no matter where you are.
- Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.
- Embrace Flexibility Benefits are best when you have the space to use them. That’s why we facilitate a flexible environment so you can find the right balance for you.
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What This Job Offers
Job Type
Full-time
Career Level
Principal
Education Level
Ph.D. or professional degree
