PE Logic Design

Rambus • Hillsboro, OR

5h • Hybrid

About The Position

Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Principal Engineer Logic Design to join our Silicon IP team in Hillsboro, Oregon. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer.
Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.

Requirements

• Strong System Verilog/Verilog RTL design expertise
• Questa/Incisive/VCS simulator experience
• Python/Perl/Tcl scripting experience
• Significant ASIC and/or FPGA design experience
• Ability to learn quickly and work independently
• Solid communication and project management skills
• 8+ years of logic design experience
• BSEE

Nice To Haves

• ASIC synthesis, timing constraint, CDC/RDC experience
• Verification experience
• Memory (HBM, GDDR, LPDDR, DDR) or MIPI expertise
• AMBA AXI or CHI design experience
• Located in the Portland, Oregon area

Responsibilities

• Design architecting and trade-off analysis
• RTL coding and verification
• Controller + PHY integration and verification
• FPGA targeting
• Customer delivery and support

Benefits

• competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level