Principal Engineer - Hardware Systems Architect

Ayar LabsSan Jose, CA
62d$180,000 - $260,000Onsite

About The Position

Ayar Labs is seeking a Principal Hardware Systems Architect to help us revolutionize photonic interconnects for high performance computing. The exceptional candidate will be highly motivated and energetic, willing to collaborate and manage communication with diverse, cross-functional teams. The primary responsibility of the Hardware Systems Architect will be to ensure the success of validation hardware for the next generation of co-packaged silicon photonics solutions. The candidate does not need prior experience in photonics but should display the propensity to learn and grow. Ayar Labs is a highly collaborative environment; the successful candidate will be organized and communicative.

Requirements

  • Advanced degree in Electrical Engineering or related field plus 12 years of industry experience
  • Demonstrated experience in designing and maintaining validation hardware systems for low-DPPM VLSI products
  • Exceptional understanding of EM, with experience in solving critical SI/PI problems
  • Proficiency in embedded systems design, with experience in full-stack development
  • Exceptional knowledge of SerDes system design

Nice To Haves

  • Experience in HDBU substrate design and validation
  • Experience in optical transceiver design and validation
  • PhD in Electrical Engineering or related field
  • Experience managing cross-functional teams
  • Firmware/Software design experience

Responsibilities

  • Design and develop hardware architecture for silicon validation.
  • Design and develop robust embedded systems architecture for silicon validation.
  • Maintain technical documentation to ensure effective communication across multi-disciplinary teams.
  • Provide mentorship to engineering staff throughout project execution.
  • Collaborate with both engineering and program management to make accurate risk assessments, driving critical project schedule.
  • Ensure the success of validation activities by reviewing test plans and technical documentation outputs.
  • Ensure appropriate standards for DFT and DFM are met across hardware engineering deliverables.

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What This Job Offers

Job Type

Full-time

Career Level

Mid Level

Industry

Publishing Industries

Number of Employees

101-250 employees

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