Principal Engineer - DRAM Design Rule
About The Position
Lead efforts to develop and refine Design Rules, Requirements, and Test Structures for all DRAM generations. Manage test structure evaluation to support next-gen device development and quantify process margins. Define sub-milestones within layout schedules and ensure timely execution across teams. Address process window vs. die size issues arising from database layout techniques. Collaborate with Design, Product Engineering, Process Integration, Business Units, and Quality teams to optimize PPAC (Performance, Power, Area, Cost). Ensure robust Design Rule Checks (DRC) and appropriate responses to deviations. Strategically partner with teams to resolve process issues related to layout and prioritize solutions. Document and communicate complex problem resolutions and drive cross-node design rule alignment. Maintain effective communication across Process Integration, Product Engineering, Design, and Advanced Mask teams. Improve documentation of R&D activities for design rule improvement Ability to define and implement design rules within APR workflows to enhance layout efficiency and manufacturability. BS/MS/PhD in Electrical Engineering, Microelectronics, Physics or related field Senior level engineer with 5 - 10+ years of experience in the semiconductor industry in the areas of Process Integration, Yield Enhancement, Product Engineering, Design, Test Structure Development, or Unit Process Development Experience with Test Structure Design and characterization Possess a deep understanding of the DRAM process flow, as well as the function and purpose of major DRAM components, such as Sense Amp, Word-line driver, and Anti-Fuse Exposure and familiarity with CAD group interactions, data post-processing, and the process of transferring data from the database to the reticle Solid grasp and exposure to design & layout with the ability to do minor layout, work with Pcells is desired Think and communicate clearly in urgent and stressful situations Demonstrated success in resolving sophisticated issues
Requirements
- BS/MS/PhD in Electrical Engineering, Microelectronics, Physics or related field
- Senior level engineer with 5 - 10+ years of experience in the semiconductor industry in the areas of Process Integration, Yield Enhancement, Product Engineering, Design, Test Structure Development, or Unit Process Development
- Experience with Test Structure Design and characterization
- Possess a deep understanding of the DRAM process flow, as well as the function and purpose of major DRAM components, such as Sense Amp, Word-line driver, and Anti-Fuse
- Exposure and familiarity with CAD group interactions, data post-processing, and the process of transferring data from the database to the reticle
- Think and communicate clearly in urgent and stressful situations
- Demonstrated success in resolving sophisticated issues
Nice To Haves
- Solid grasp and exposure to design & layout with the ability to do minor layout, work with Pcells is desired
Responsibilities
- Develop and refine Design Rules, Requirements, and Test Structures for all DRAM generations
- Manage test structure evaluation to support next-gen device development and quantify process margins
- Define sub-milestones within layout schedules and ensure timely execution across teams
- Address process window vs. die size issues arising from database layout techniques
- Collaborate with Design, Product Engineering, Process Integration, Business Units, and Quality teams to optimize PPAC (Performance, Power, Area, Cost)
- Ensure robust Design Rule Checks (DRC) and appropriate responses to deviations
- Strategically partner with teams to resolve process issues related to layout and prioritize solutions
- Document and communicate complex problem resolutions and drive cross-node design rule alignment
- Maintain effective communication across Process Integration, Product Engineering, Design, and Advanced Mask teams
- Improve documentation of R&D activities for design rule improvement
- Define and implement design rules within APR workflows to enhance layout efficiency and manufacturability
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What This Job Offers
Job Type
Full-time
Career Level
Senior
Education Level
Ph.D. or professional degree
Number of Employees
5,001-10,000 employees
