Principal Engineer, Design For Test

Marvell Technology•Westborough, MA

21h

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Digital IC Design Principal Engineer with Marvell, you’ll be a member of the Custom Silicon Engineering team. This team is a leader in large multi-die designs that are driving high compute performance and acceleration in many markets, including custom AI, 5G and 6G. The role will be challenging and will require an experienced DFT engineer that can work with existing DFT solutions while also creating new solutions to address industry first issues. What You Can Expect The position will be responsible for architecting, leading and implementing DFT/Test on complex IP and SOC for multiple custom/compute ASIC/SoC designs. The execution involves Design-for-Test architecture definition, implementation of various DFT/DFX features, validation, IP-DFT, STA, pattern generation & post-silicon bring-up and debug for various designs/IPs in Custom/Compute space. In this position, the responsibility also includes mentoring, guiding and driving a small team of engineers to enable their development and ability to scale across multiple designs. The position also involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test. What We're Looking For Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience. Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience. Direct DFT experience with at least 10 years in the custom chip design business. Hands on working experience in various stages of DFT-Execution - SCAN/MBIST/Validation/STA/IP-DFX/Post-Silicon Bringup/Debug. Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at least one SoC Design. Understanding of DFT Flows and Methodologies and Experience. Prior experience in leading ASIC designs. Expected Base Pay Range (USD) 148,500 - 219,780, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected]. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-AO1 Join our talent community to hear about company news, job openings and events. Join our Talent Community! Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Recruitment fraud is a well-known way that third parties try to get personal information or to steal money from you. Please review Marvell’s guidance here to learn more on how you can protect yourself.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience.
Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
Direct DFT experience with at least 10 years in the custom chip design business.
Hands on working experience in various stages of DFT-Execution - SCAN/MBIST/Validation/STA/IP-DFX/Post-Silicon Bringup/Debug.
Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at least one SoC Design.
Understanding of DFT Flows and Methodologies and Experience.
Prior experience in leading ASIC designs.

Responsibilities

architecting, leading and implementing DFT/Test on complex IP and SOC for multiple custom/compute ASIC/SoC designs
Design-for-Test architecture definition
implementation of various DFT/DFX features
validation
IP-DFT
STA
pattern generation & post-silicon bring-up and debug for various designs/IPs in Custom/Compute space
mentoring, guiding and driving a small team of engineers to enable their development and ability to scale across multiple designs
definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test