Principal Engineer, ASIC Design Verification

Ayar Labs • San Jose, CA

62d • Onsite

About The Position

We are seeking a Principal Design Verification Engineer to lead the verification strategy for our next-generation silicon photonic chip. In this role, you will serve as a technical lead, architecting scalable verification environments and driving high-quality silicon from concept to tape-out. You will look beyond block-level testing to solve complex system-level challenges, define methodologies, and mentor a growing team of bright engineers.

Requirements

• Experience: MS in Electrical Engineering, Computer Engineering, or related field with 12+ years of relevant experience in ASIC/SoC verification.
• Core Competency: Expert-level proficiency in SystemVerilog and UVM (Universal Verification Methodology).
• Architecture: Proven track record of building verification environments from scratch (Agents, Scoreboards, Sequencers, etc.).
• Protocols: Deep knowledge of standard interface protocols (PCIe, ARM MCU, AMBA/AXI, UCIe).
• Scripting: Strong proficiency in scripting languages for automation (Python, Perl, Tcl, or Shell).
• Coverage: Experience defining functional coverage groups and driving logic verification to 100% closure.

Nice To Haves

• Formal Verification: Experience with formal property checking (VC Formal) and writing SVA (SystemVerilog Assertions).
• Emulation & Acceleration: Hands-on experience with hardware emulation platforms.
• Processor Knowledge: Familiarity with RISC-V or ARM architecture and coherency protocols.
• Mixed Signal: Experience in Analog/Mixed-Signal (AMS) verification.
• Modeling: Experience with C/C++ or SystemC modeling for reference models.
• Experience working on digital designs with multiple clock domains and clock dividers
• Experience in verification of SerDes IP block interfaces in a complex SoC fabric environment
• Experience in verification of the PCS, PMA SerDes layers and internal SerDes digital backends
• Experience with verification of HBM memory interfaces (PHY and controller)
• Experience in formal model equivalence checking tools and verification methodology
• Programming experience in Python

Responsibilities

• Architect Testbenches: Define and build modular, reusable, and scalable UVM testbench architectures for complex IP blocks and Sub-systems.
• Drive Methodology: Set the standard for verification methodologies, coding guidelines, and coverage metrics. Evaluate and deploy new EDA tools, formal verification techniques, or emulation flows.
• Strategic Planning: Collaborate with Architects and RTL Designers early in the cycle to define the verification plan, identify architectural bottlenecks, and ensure micro-architecture testability.
• Complex Debugging: Lead the effort to debug elusive hardware bugs, root-causing issues across RTL, firmware, and the verification environment.
• Technical Leadership: Mentor senior and junior engineers, conduct code reviews, and foster a culture of engineering excellence.
• Automation & Efficiency: Develop scripts and infrastructure to automate regression testing, performance analysis, and coverage closure.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Number of Employees: 101-250 employees