Principal Engineer, AI Compute and Chiplet Systems Technologist

Qualcomm•San Diego, CA

27d•$192,000 - $288,000

About The Position

We are seeking a highly skilled and experienced engineer to develop system-technology co-optimized solutions for the slowing Moore’s law era. The focus is on identifying and driving individual process technology components to achieve the best E2E system KPIs of AI and other emerging workloads scalable across different BUs. Multiple and varied individual technology components and their interactions across the system stack drive the E2E system KPIs. The E2E system KPIs for AI and emerging workloads include the power, performance and TCO of the entire system. The underlying technology components driving the E2E KPIs are as varied as tech node compute IPs, SRAM, DRAM, NVM multi-hierarchical memories, electrical and optical networking, 2.5D/ 3D/3.5D chiplets. The primary role of the candidate is to comprehend these individual components and the way they interact to deliver the best system solution. The candidate also needs to make sure that the solutions are scalable across different business units (BUs) from datacenters to physical AI to computing devices. To drive these technologies the person will collaborate with high-level representatives across functional teams (e.g. Architecture, product management, Design teams) and external (Foundry, Memory vendors) to develop and execute an implementation strategy that meets system requirements.

Requirements

Thorough understanding of E2E system KPI dependency e.g. power, performance and TCO on the underlying process technology components and the ability to identify and drive the key individual process components and architectures.
Good knowledge of underlying components e.g. tech node, logic IPs, SRAM, DRAM, NVM memory architecture, electrical and optical networking and 2.5D, 3D, 3.5D integration schemes and their interactions and trade-offs for E2E KPI optimization.
Ability to model and script (with internal/ external tools) the system use case impact of 3D, 3.5D integration of process tech node logic, 3D SRAM and DRAM architectures and networking (electrical and optical).
Ability to map emerging system use cases to hardware, chiplet and process architecture solutions; and vice versa
Exceptional creativity to innovate new ideas and develop innovative products/ processes without established objectives or known parameters.
Verbal and written communication skills to convey highly complex and/or detailed information. Will require strong negotiation and influence with large groups or high-level constituents
Ability to work independently and as part of a team
Most tasks do not have defined steps; simultaneous use of multiple mental abilities is generally required to determine the best approach
Deductive and inductive problem solving is required; multiple approaches may be taken/necessary to solve the problem; often information is missing or conflicting; advanced data analysis and interpretation skills are required.
Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.

Nice To Haves

Master's or Ph.D. in Electrical Engineering, Computer Science, or a related field
12+ years of ASIC design, verification, validation, integration, or related work experience.
4+ years of experience with architecture and design tools.
4+ years of experience with scripting tools and programming languages.
4+ years of experience with design verification methods.
2+ years of work experience in a role requiring interaction with senior leadership (e.g., Vice President level and above).

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