Principal DSP Engineer

Marvell•Santa Clara, CA

30d

About The Position

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell's Architecture team leads the industry in wireline Ethernet communication technologies, delivering solutions for applications ranging from hyperscale data center interconnects to industrial PHYs. Their portfolio spans speeds up to 1.6 Tb/s and supports diverse media types, including optical fibers, high-speed coaxial cables, and shielded/unshielded twisted pair cables. The underlying core technologies that enable these products are state of the art of equalization techniques like Maximum likelihood sequence estimation, timing synchronization, cross talk and echo cancellation techniques, error control coding techniques such as LDPC, product and concatenated codes, combined with architectural and circuit innovations to enable low power high speed implementation of these complex algorithms. Come join Marvell to work on the DSP and architecture challenges that need to be solved to enable products and technologies that will determine the future direction for the entire industry.

Requirements

Ph.D., or M.S. in Electrical Engineering, Computer Science or related fields and 3+ years of related design experience. Strong knowledge of communications theory and system design, and digital signal processing.
Proficient in C/C++ and Matlab or Python.
Familiarity with Ethernet systems is a plus.
Experience in high-speed DSP, especially FFE/DFE, Clock and Data Recovery (CDR) or FEC (RS, soft decoding, Viterbi algorithm) is a big plus.
Experience with ADC-based wireline transceivers and/or coherent DSP architectures is a plus.
Experience with high-speed/time interleaved ADC and the associated calibration algorithms is a plus
Team player, willing to take on a variety of projects, good listening skills, self-motivated.

Responsibilities

Design and simulate DSP architectures, define key capabilities, performance requirements and drive specifications for both analog and digital designers.
Create DSP and FEC hardware block specifications appropriate for RTL implementation.
Perform research activities in digital signal processing for Base-T, SerDes and optical channels
Work with designers to ensure circuit architecture can be efficiently implemented.
Develop/perform behavioral modeling of mixed-signal circuit designs for transceivers.
Provide guidance on test plans for lab characterization once design comes back from fab.
Participate in chip lab bring up. Should be comfortable working with lab equipment.