Principal Digital ASIC Design Engineer

K2 Space

6h•$190,000 - $285,000

About The Position

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply. The Role We are seeking a highly skilled Principal Digital ASIC Design Engineer to lead the design and implementation of digital subsystems for advanced wireless SoCs. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will architect, develop, and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have flown your sub-system in space and developed cutting-edge mixed-signal SoCs.

Requirements

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
10+ years of relevant industry experience in digital ASIC design, with significant ownership of complex subsystems.
Proficiency in RTL design (SystemVerilog or Verilog), synthesis, and linting tools.
Experience in micro-architecture definition from architecture guideline and model analysis.
Experience in closing full-chip and subsystem timing working with synthesis and static analysis teams.
Experience with DFT tools for scan and BIST insertion.
Solid understanding of SoC design flows including clock/power domain crossing, timing constraints, and formal verification.
Experience developing and integrating DSP blocks for wireless communication (e.g. OFDM, MIMO, channel estimation, DFE, etc.).
Strong experience with EDA tools for design, synthesis, static timing analysis, and power analysis (e.g. Synopsys, Cadence, Siemens tools).
Strong debugging, problem-solving, and communication skills.

Nice To Haves

Prior experience in wireless SoC development (e.g. cellular, Wi-Fi, satellite, or mmWave systems) and successful tapeouts in advanced design nodes.
Design experience in datapath, flow control, arbitration, FIFO, DMA, IOMMU, SoC bus architecture, ARM’s AXI/AHB bus architecture & protocols, serial interfaces such as SPI, I3C, UART.
Familiarity with DSP algorithm modeling (MATLAB, Python, or C++) and converting models into RTL.
Experience working with FEC, baseband PHYs, or digital beamforming architectures.
Knowledge of digital calibration and control of RF/mixed-signal front ends.
Exposure to hardware-software co-design and embedded process integration.
Experience working in cross-functional, geographically distributed teams.

Responsibilities

Own the architecture, microarchitecture, RTL implementation, and integration of key digital blocks in wireless SoCs.
Collaborate with system architects to translate high-level DSP algorithms into efficient hardware implementations.
Drive end-to-end development of DSP systems (e.g., filters, beamformers, FFT/IFFT engines).
Convert chip specifications into RTL using internal IPs and external IPs.
Design and develop RTL for interfaces, power management, clocking, reset, test & debug.
Partner with analog/mixed-signal teams to define digital-analog interfaces, calibration engines, and control logic.
Optimize designs for power, performance, and area (PPA) and support timing closure through synthesis and backend collaboration.
Lead or contribute to verification planning and validation of complex digital subsystems.
Participate in chip bring-up and lab validation of complex digital subsystems.
Support your product through production and spaceflight.
Act as a technical leader and subject-matter expert, helping to teach, grow, and mentor others in the team.